|
[-]
[+]
|
Changed |
_service:tar_git:libdrm.changes
|
|
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm.spec
^
|
|
|
|
[-]
[+]
|
Changed |
_service
^
|
| @@ -1,7 +1,8 @@
<services>
<service name="tar_git">
- <param name="url">https://github.com/sailfish-on-dontbeevil/libdrm</param>
+ <param name="url">https://github.com/sailfishos/libdrm</param>
<param name="branch">master</param>
+ <param name="revision">2.4.115+git1</param>
<param name="token"/>
<param name="debian">N</param>
<param name="dumb">N</param>
|
|
[-]
[+]
|
Deleted |
_service:tar_git:libdrm-2.4.110+git1.tar.bz2/upstream/.gitlab-ci/debian-install.sh
^
|
| @@ -1,66 +0,0 @@
-#!/usr/bin/env bash
-set -o errexit
-set -o xtrace
-
-export DEBIAN_FRONTEND=noninteractive
-
-CROSS_ARCHITECTURES=(i386 armhf arm64 ppc64el)
-for arch in ${CROSS_ARCHITECTURES[@]}; do
- dpkg --add-architecture $arch
-done
-
-apt-get install -y \
- ca-certificates
-
-sed -i -e 's/http:\/\/deb/https:\/\/deb/g' /etc/apt/sources.list
-echo 'deb https://deb.debian.org/debian buster-backports main' >/etc/apt/sources.list.d/backports.list
-
-apt-get update
-
-# Use newer packages from backports by default
-cat >/etc/apt/preferences <<EOF
-Package: *
-Pin: release a=buster-backports
-Pin-Priority: 500
-EOF
-
-apt-get dist-upgrade -y
-
-apt-get install -y --no-remove \
- build-essential \
- docbook-xsl \
- libatomic-ops-dev \
- libcairo2-dev \
- libcunit1-dev \
- libpciaccess-dev \
- meson \
- ninja-build \
- pkg-config \
- python3 \
- python3-pip \
- python3-wheel \
- python3-setuptools \
- python3-docutils \
- valgrind
-
-for arch in ${CROSS_ARCHITECTURES[@]}; do
- cross_file=/cross_file-$arch.txt
-
- # Cross-build libdrm deps
- apt-get install -y --no-remove \
- libcairo2-dev:$arch \
- libpciaccess-dev:$arch \
- crossbuild-essential-$arch
-
- # Generate cross build files for Meson
- /usr/share/meson/debcrossgen --arch $arch -o $cross_file
-
- # Work around a bug in debcrossgen that should be fixed in the next release
- if [ $arch = i386 ]; then
- sed -i "s|cpu_family = 'i686'|cpu_family = 'x86'|g" $cross_file
- fi
-done
-
-
-# Test that the oldest Meson version we claim to support is still supported
-pip3 install meson==0.46
|
|
[-]
[+]
|
Deleted |
_service:tar_git:libdrm-2.4.110+git1.tar.bz2/upstream/intel/i915_pciids.h
^
|
| @@ -1,684 +0,0 @@
-/*
- * Copyright 2013 Intel Corporation
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-#ifndef _I915_PCIIDS_H
-#define _I915_PCIIDS_H
-
-/*
- * A pci_device_id struct {
- * __u32 vendor, device;
- * __u32 subvendor, subdevice;
- * __u32 class, class_mask;
- * kernel_ulong_t driver_data;
- * };
- * Don't use C99 here because "class" is reserved and we want to
- * give userspace flexibility.
- */
-#define INTEL_VGA_DEVICE(id, info) { \
- 0x8086, id, \
- ~0, ~0, \
- 0x030000, 0xff0000, \
- (unsigned long) info }
-
-#define INTEL_QUANTA_VGA_DEVICE(info) { \
- 0x8086, 0x16a, \
- 0x152d, 0x8990, \
- 0x030000, 0xff0000, \
- (unsigned long) info }
-
-#define INTEL_I810_IDS(info) \
- INTEL_VGA_DEVICE(0x7121, info), /* I810 */ \
- INTEL_VGA_DEVICE(0x7123, info), /* I810_DC100 */ \
- INTEL_VGA_DEVICE(0x7125, info) /* I810_E */
-
-#define INTEL_I815_IDS(info) \
- INTEL_VGA_DEVICE(0x1132, info) /* I815*/
-
-#define INTEL_I830_IDS(info) \
- INTEL_VGA_DEVICE(0x3577, info)
-
-#define INTEL_I845G_IDS(info) \
- INTEL_VGA_DEVICE(0x2562, info)
-
-#define INTEL_I85X_IDS(info) \
- INTEL_VGA_DEVICE(0x3582, info), /* I855_GM */ \
- INTEL_VGA_DEVICE(0x358e, info)
-
-#define INTEL_I865G_IDS(info) \
- INTEL_VGA_DEVICE(0x2572, info) /* I865_G */
-
-#define INTEL_I915G_IDS(info) \
- INTEL_VGA_DEVICE(0x2582, info), /* I915_G */ \
- INTEL_VGA_DEVICE(0x258a, info) /* E7221_G */
-
-#define INTEL_I915GM_IDS(info) \
- INTEL_VGA_DEVICE(0x2592, info) /* I915_GM */
-
-#define INTEL_I945G_IDS(info) \
- INTEL_VGA_DEVICE(0x2772, info) /* I945_G */
-
-#define INTEL_I945GM_IDS(info) \
- INTEL_VGA_DEVICE(0x27a2, info), /* I945_GM */ \
- INTEL_VGA_DEVICE(0x27ae, info) /* I945_GME */
-
-#define INTEL_I965G_IDS(info) \
- INTEL_VGA_DEVICE(0x2972, info), /* I946_GZ */ \
- INTEL_VGA_DEVICE(0x2982, info), /* G35_G */ \
- INTEL_VGA_DEVICE(0x2992, info), /* I965_Q */ \
- INTEL_VGA_DEVICE(0x29a2, info) /* I965_G */
-
-#define INTEL_G33_IDS(info) \
- INTEL_VGA_DEVICE(0x29b2, info), /* Q35_G */ \
- INTEL_VGA_DEVICE(0x29c2, info), /* G33_G */ \
- INTEL_VGA_DEVICE(0x29d2, info) /* Q33_G */
-
-#define INTEL_I965GM_IDS(info) \
- INTEL_VGA_DEVICE(0x2a02, info), /* I965_GM */ \
- INTEL_VGA_DEVICE(0x2a12, info) /* I965_GME */
-
-#define INTEL_GM45_IDS(info) \
- INTEL_VGA_DEVICE(0x2a42, info) /* GM45_G */
-
-#define INTEL_G45_IDS(info) \
- INTEL_VGA_DEVICE(0x2e02, info), /* IGD_E_G */ \
- INTEL_VGA_DEVICE(0x2e12, info), /* Q45_G */ \
- INTEL_VGA_DEVICE(0x2e22, info), /* G45_G */ \
- INTEL_VGA_DEVICE(0x2e32, info), /* G41_G */ \
- INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \
- INTEL_VGA_DEVICE(0x2e92, info) /* B43_G.1 */
-
-#define INTEL_PINEVIEW_G_IDS(info) \
- INTEL_VGA_DEVICE(0xa001, info)
-
-#define INTEL_PINEVIEW_M_IDS(info) \
- INTEL_VGA_DEVICE(0xa011, info)
-
-#define INTEL_IRONLAKE_D_IDS(info) \
- INTEL_VGA_DEVICE(0x0042, info)
-
-#define INTEL_IRONLAKE_M_IDS(info) \
- INTEL_VGA_DEVICE(0x0046, info)
-
-#define INTEL_SNB_D_GT1_IDS(info) \
- INTEL_VGA_DEVICE(0x0102, info), \
- INTEL_VGA_DEVICE(0x010A, info)
-
-#define INTEL_SNB_D_GT2_IDS(info) \
- INTEL_VGA_DEVICE(0x0112, info), \
- INTEL_VGA_DEVICE(0x0122, info)
-
-#define INTEL_SNB_D_IDS(info) \
- INTEL_SNB_D_GT1_IDS(info), \
- INTEL_SNB_D_GT2_IDS(info)
-
-#define INTEL_SNB_M_GT1_IDS(info) \
- INTEL_VGA_DEVICE(0x0106, info)
-
-#define INTEL_SNB_M_GT2_IDS(info) \
- INTEL_VGA_DEVICE(0x0116, info), \
- INTEL_VGA_DEVICE(0x0126, info)
-
-#define INTEL_SNB_M_IDS(info) \
- INTEL_SNB_M_GT1_IDS(info), \
- INTEL_SNB_M_GT2_IDS(info)
-
-#define INTEL_IVB_M_GT1_IDS(info) \
- INTEL_VGA_DEVICE(0x0156, info) /* GT1 mobile */
-
-#define INTEL_IVB_M_GT2_IDS(info) \
- INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */
-
-#define INTEL_IVB_M_IDS(info) \
- INTEL_IVB_M_GT1_IDS(info), \
- INTEL_IVB_M_GT2_IDS(info)
-
-#define INTEL_IVB_D_GT1_IDS(info) \
- INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \
- INTEL_VGA_DEVICE(0x015a, info) /* GT1 server */
-
-#define INTEL_IVB_D_GT2_IDS(info) \
- INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \
- INTEL_VGA_DEVICE(0x016a, info) /* GT2 server */
-
-#define INTEL_IVB_D_IDS(info) \
- INTEL_IVB_D_GT1_IDS(info), \
- INTEL_IVB_D_GT2_IDS(info)
-
-#define INTEL_IVB_Q_IDS(info) \
- INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
-
-#define INTEL_HSW_ULT_GT1_IDS(info) \
- INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
- INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
- INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
- INTEL_VGA_DEVICE(0x0A0B, info) /* ULT GT1 reserved */
-
-#define INTEL_HSW_ULX_GT1_IDS(info) \
- INTEL_VGA_DEVICE(0x0A0E, info) /* ULX GT1 mobile */
-
-#define INTEL_HSW_GT1_IDS(info) \
- INTEL_HSW_ULT_GT1_IDS(info), \
- INTEL_HSW_ULX_GT1_IDS(info), \
- INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
- INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
- INTEL_VGA_DEVICE(0x040A, info), /* GT1 server */ \
- INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
- INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \
- INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \
- INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
- INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
- INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
- INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
- INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
- INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \
- INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
- INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
- INTEL_VGA_DEVICE(0x0D0E, info) /* CRW GT1 reserved */
-
-#define INTEL_HSW_ULT_GT2_IDS(info) \
|
|
[-]
[+]
|
Deleted |
_service:tar_git:libdrm-2.4.110+git1.tar.bz2/upstream/intel/intel_chipset.c
^
|
| @@ -1,94 +0,0 @@
-/*
- * Copyright (C) 2018 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-#include "intel_chipset.h"
-
-#include <inttypes.h>
-#include <stdbool.h>
-
-#include "i915_pciids.h"
-
-#undef INTEL_VGA_DEVICE
-#define INTEL_VGA_DEVICE(id, gen) { id, gen }
-
-static const struct pci_device {
- uint16_t device;
- uint16_t gen;
-} pciids[] = {
- /* Keep ids sorted by gen; latest gen first */
- INTEL_RPLS_IDS(12),
- INTEL_ADLN_IDS(12),
- INTEL_ADLP_IDS(12),
- INTEL_ADLS_IDS(12),
- INTEL_RKL_IDS(12),
- INTEL_DG1_IDS(12),
- INTEL_TGL_12_IDS(12),
- INTEL_JSL_IDS(11),
- INTEL_EHL_IDS(11),
- INTEL_ICL_11_IDS(11),
- INTEL_CNL_IDS(10),
- INTEL_CFL_IDS(9),
- INTEL_GLK_IDS(9),
- INTEL_KBL_IDS(9),
- INTEL_BXT_IDS(9),
- INTEL_SKL_IDS(9),
-};
-
-drm_private bool intel_is_genx(unsigned int devid, int gen)
-{
- const struct pci_device *p,
- *pend = pciids + sizeof(pciids) / sizeof(pciids[0]);
-
- for (p = pciids; p < pend; p++) {
- /* PCI IDs are sorted */
- if (p->gen < gen)
- break;
-
- if (p->device != devid)
- continue;
-
- if (gen == p->gen)
- return true;
-
- break;
- }
-
- return false;
-}
-
-drm_private bool intel_get_genx(unsigned int devid, int *gen)
-{
- const struct pci_device *p,
- *pend = pciids + sizeof(pciids) / sizeof(pciids[0]);
-
- for (p = pciids; p < pend; p++) {
- if (p->device != devid)
- continue;
-
- if (gen)
- *gen = p->gen;
-
- return true;
- }
-
- return false;
-}
|
|
[-]
[+]
|
Deleted |
_service:tar_git:libdrm-2.4.110+git1.tar.bz2/upstream/libkms/Android.mk
^
|
| @@ -1,51 +0,0 @@
-DRM_GPU_DRIVERS := $(strip $(filter-out swrast, $(BOARD_GPU_DRIVERS)))
-
-intel_drivers := i915 i965 i915g iris
-radeon_drivers := r300g r600g radeonsi
-nouveau_drivers := nouveau
-virgl_drivers := virgl
-vmwgfx_drivers := vmwgfx
-
-valid_drivers := \
- $(intel_drivers) \
- $(radeon_drivers) \
- $(nouveau_drivers) \
- $(virgl_drivers) \
- $(vmwgfx_drivers)
-
-# warn about invalid drivers
-invalid_drivers := $(filter-out $(valid_drivers), $(DRM_GPU_DRIVERS))
-ifneq ($(invalid_drivers),)
-$(warning invalid GPU drivers: $(invalid_drivers))
-# tidy up
-DRM_GPU_DRIVERS := $(filter-out $(invalid_drivers), $(DRM_GPU_DRIVERS))
-endif
-
-LOCAL_PATH := $(call my-dir)
-
-include $(CLEAR_VARS)
-include $(LOCAL_PATH)/Makefile.sources
-
-LOCAL_SRC_FILES := $(LIBKMS_FILES)
-
-ifneq ($(filter $(vmwgfx_drivers), $(DRM_GPU_DRIVERS)),)
-LOCAL_SRC_FILES += $(LIBKMS_VMWGFX_FILES)
-endif
-
-ifneq ($(filter $(intel_drivers), $(DRM_GPU_DRIVERS)),)
-LOCAL_SRC_FILES += $(LIBKMS_INTEL_FILES)
-endif
-
-ifneq ($(filter $(nouveau_drivers), $(DRM_GPU_DRIVERS)),)
-LOCAL_SRC_FILES += $(LIBKMS_NOUVEAU_FILES)
-endif
-
-ifneq ($(filter $(radeon_drivers), $(DRM_GPU_DRIVERS)),)
-LOCAL_SRC_FILES += $(LIBKMS_RADEON_FILES)
-endif
-
-LOCAL_MODULE := libkms
-LOCAL_SHARED_LIBRARIES := libdrm
-
-include $(LIBDRM_COMMON_MK)
-include $(BUILD_SHARED_LIBRARY)
|
|
[-]
[+]
|
Deleted |
_service:tar_git:libdrm-2.4.110+git1.tar.bz2/upstream/libkms/Makefile.sources
^
|
| @@ -1,23 +0,0 @@
-LIBKMS_FILES := \
- internal.h \
- linux.c \
- dumb.c \
- api.c
-
-LIBKMS_VMWGFX_FILES := \
- vmwgfx.c
-
-LIBKMS_INTEL_FILES := \
- intel.c
-
-LIBKMS_NOUVEAU_FILES := \
- nouveau.c
-
-LIBKMS_RADEON_FILES := \
- radeon.c
-
-LIBKMS_EXYNOS_FILES := \
- exynos.c
-
-LIBKMS_H_FILES := \
- libkms.h
|
|
[-]
[+]
|
Deleted |
_service:tar_git:libdrm-2.4.110+git1.tar.bz2/upstream/libkms/api.c
^
|
| @@ -1,139 +0,0 @@
-/**************************************************************************
- *
- * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- **************************************************************************/
-
-
-#include <errno.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "libdrm_macros.h"
-#include "internal.h"
-
-drm_public int kms_create(int fd, struct kms_driver **out)
-{
- return linux_create(fd, out);
-}
-
-drm_public int kms_get_prop(struct kms_driver *kms, unsigned key, unsigned *out)
-{
- switch (key) {
- case KMS_BO_TYPE:
- break;
- default:
- return -EINVAL;
- }
- return kms->get_prop(kms, key, out);
-}
-
-drm_public int kms_destroy(struct kms_driver **kms)
-{
- if (!(*kms))
- return 0;
-
- free(*kms);
- *kms = NULL;
- return 0;
-}
-
-drm_public int kms_bo_create(struct kms_driver *kms, const unsigned *attr, struct kms_bo **out)
-{
- unsigned width = 0;
- unsigned height = 0;
- enum kms_bo_type type = KMS_BO_TYPE_SCANOUT_X8R8G8B8;
- int i;
-
- for (i = 0; attr[i];) {
- unsigned key = attr[i++];
- unsigned value = attr[i++];
-
- switch (key) {
- case KMS_WIDTH:
- width = value;
- break;
- case KMS_HEIGHT:
- height = value;
- break;
- case KMS_BO_TYPE:
- type = value;
- break;
- default:
- return -EINVAL;
- }
- }
-
- if (width == 0 || height == 0)
- return -EINVAL;
-
- /* XXX sanity check type */
-
- if (type == KMS_BO_TYPE_CURSOR_64X64_A8R8G8B8 &&
- (width != 64 || height != 64))
- return -EINVAL;
-
- return kms->bo_create(kms, width, height, type, attr, out);
-}
-
-drm_public int kms_bo_get_prop(struct kms_bo *bo, unsigned key, unsigned *out)
-{
- switch (key) {
- case KMS_PITCH:
- *out = bo->pitch;
- break;
- case KMS_HANDLE:
- *out = bo->handle;
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-drm_public int kms_bo_map(struct kms_bo *bo, void **out)
-{
- return bo->kms->bo_map(bo, out);
-}
-
-drm_public int kms_bo_unmap(struct kms_bo *bo)
-{
- return bo->kms->bo_unmap(bo);
-}
-
-drm_public int kms_bo_destroy(struct kms_bo **bo)
-{
- int ret;
-
- if (!(*bo))
- return 0;
-
- ret = (*bo)->kms->bo_destroy(*bo);
- if (ret)
- return ret;
-
- *bo = NULL;
- return 0;
-}
|
|
[-]
[+]
|
Deleted |
_service:tar_git:libdrm-2.4.110+git1.tar.bz2/upstream/libkms/dumb.c
^
|
| @@ -1,216 +0,0 @@
-/**************************************************************************
- *
- * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- **************************************************************************/
-
-
-#include <errno.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include "internal.h"
-
-#include <sys/ioctl.h>
-#include "xf86drm.h"
-#include "libdrm_macros.h"
-
-struct dumb_bo
-{
- struct kms_bo base;
- unsigned map_count;
-};
-
-static int
-dumb_get_prop(struct kms_driver *kms, unsigned key, unsigned *out)
-{
- switch (key) {
- case KMS_BO_TYPE:
- *out = KMS_BO_TYPE_SCANOUT_X8R8G8B8 | KMS_BO_TYPE_CURSOR_64X64_A8R8G8B8;
- break;
- default:
- return -EINVAL;
- }
- return 0;
-}
-
-static int
-dumb_destroy(struct kms_driver *kms)
-{
- free(kms);
- return 0;
-}
-
-static int
-dumb_bo_create(struct kms_driver *kms,
- const unsigned width, const unsigned height,
- const enum kms_bo_type type, const unsigned *attr,
- struct kms_bo **out)
-{
- struct drm_mode_create_dumb arg;
- struct dumb_bo *bo;
- int i, ret;
-
- for (i = 0; attr[i]; i += 2) {
- switch (attr[i]) {
- case KMS_WIDTH:
- case KMS_HEIGHT:
- break;
- case KMS_BO_TYPE:
- break;
- default:
- return -EINVAL;
- }
- }
-
- bo = calloc(1, sizeof(*bo));
- if (!bo)
- return -ENOMEM;
-
- memset(&arg, 0, sizeof(arg));
-
- /* All BO_TYPE currently are 32bpp formats */
- arg.bpp = 32;
- arg.width = width;
- arg.height = height;
-
- ret = drmIoctl(kms->fd, DRM_IOCTL_MODE_CREATE_DUMB, &arg);
- if (ret)
- goto err_free;
-
- bo->base.kms = kms;
- bo->base.handle = arg.handle;
- bo->base.size = arg.size;
- bo->base.pitch = arg.pitch;
-
- *out = &bo->base;
-
- return 0;
-
-err_free:
- free(bo);
- return ret;
-}
-
-static int
-dumb_bo_get_prop(struct kms_bo *bo, unsigned key, unsigned *out)
-{
- switch (key) {
- default:
- return -EINVAL;
- }
-}
-
-static int
-dumb_bo_map(struct kms_bo *_bo, void **out)
-{
- struct dumb_bo *bo = (struct dumb_bo *)_bo;
- struct drm_mode_map_dumb arg;
- void *map = NULL;
- int ret;
-
- if (bo->base.ptr) {
- bo->map_count++;
- *out = bo->base.ptr;
- return 0;
- }
-
- memset(&arg, 0, sizeof(arg));
- arg.handle = bo->base.handle;
-
- ret = drmIoctl(bo->base.kms->fd, DRM_IOCTL_MODE_MAP_DUMB, &arg);
- if (ret)
- return ret;
-
- map = drm_mmap(0, bo->base.size, PROT_READ | PROT_WRITE, MAP_SHARED, bo->base.kms->fd, arg.offset);
- if (map == MAP_FAILED)
- return -errno;
-
- bo->base.ptr = map;
- bo->map_count++;
- *out = bo->base.ptr;
-
- return 0;
-}
-
-static int
-dumb_bo_unmap(struct kms_bo *_bo)
-{
- struct dumb_bo *bo = (struct dumb_bo *)_bo;
- bo->map_count--;
- return 0;
-}
-
-static int
-dumb_bo_destroy(struct kms_bo *_bo)
-{
- struct dumb_bo *bo = (struct dumb_bo *)_bo;
- struct drm_mode_destroy_dumb arg;
- int ret;
-
- if (bo->base.ptr) {
- /* XXX Sanity check map_count */
- drm_munmap(bo->base.ptr, bo->base.size);
- bo->base.ptr = NULL;
- }
-
- memset(&arg, 0, sizeof(arg));
- arg.handle = bo->base.handle;
-
- ret = drmIoctl(bo->base.kms->fd, DRM_IOCTL_MODE_DESTROY_DUMB, &arg);
- if (ret)
- return -errno;
-
- free(bo);
- return 0;
-}
-
-drm_private int
-dumb_create(int fd, struct kms_driver **out)
-{
- struct kms_driver *kms;
- int ret;
- uint64_t cap = 0;
-
- ret = drmGetCap(fd, DRM_CAP_DUMB_BUFFER, &cap);
- if (ret || cap == 0)
- return -EINVAL;
-
|
|
[-]
[+]
|
Deleted |
_service:tar_git:libdrm-2.4.110+git1.tar.bz2/upstream/libkms/exynos.c
^
|
| @@ -1,220 +0,0 @@
-/* exynos.c
- *
- * Copyright 2009 Samsung Electronics Co., Ltd.
- * Authors:
- * SooChan Lim <sc1.lim@samsung.com>
- * Sangjin LEE <lsj119@samsung.com>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- */
-
-#include <errno.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include "internal.h"
-
-#include <sys/mman.h>
-#include <sys/ioctl.h>
-#include "xf86drm.h"
-
-#include "libdrm_macros.h"
-#include "exynos_drm.h"
-
-struct exynos_bo
-{
- struct kms_bo base;
- unsigned map_count;
-};
-
-static int
-exynos_get_prop(struct kms_driver *kms, unsigned key, unsigned *out)
-{
- switch (key) {
- case KMS_BO_TYPE:
- *out = KMS_BO_TYPE_SCANOUT_X8R8G8B8 | KMS_BO_TYPE_CURSOR_64X64_A8R8G8B8;
- break;
- default:
- return -EINVAL;
- }
- return 0;
-}
-
-static int
-exynos_destroy(struct kms_driver *kms)
-{
- free(kms);
- return 0;
-}
-
-static int
-exynos_bo_create(struct kms_driver *kms,
- const unsigned width, const unsigned height,
- const enum kms_bo_type type, const unsigned *attr,
- struct kms_bo **out)
-{
- struct drm_exynos_gem_create arg;
- unsigned size, pitch;
- struct exynos_bo *bo;
- int i, ret;
-
- for (i = 0; attr[i]; i += 2) {
- switch (attr[i]) {
- case KMS_WIDTH:
- case KMS_HEIGHT:
- case KMS_BO_TYPE:
- break;
- default:
- return -EINVAL;
- }
- }
-
- bo = calloc(1, sizeof(*bo));
- if (!bo)
- return -ENOMEM;
-
- if (type == KMS_BO_TYPE_CURSOR_64X64_A8R8G8B8) {
- pitch = 64 * 4;
- size = 64 * 64 * 4;
- } else if (type == KMS_BO_TYPE_SCANOUT_X8R8G8B8) {
- pitch = width * 4;
- pitch = (pitch + 512 - 1) & ~(512 - 1);
- size = pitch * ((height + 4 - 1) & ~(4 - 1));
- } else {
- ret = -EINVAL;
- goto err_free;
- }
-
- memset(&arg, 0, sizeof(arg));
- arg.size = size;
-
- ret = drmCommandWriteRead(kms->fd, DRM_EXYNOS_GEM_CREATE, &arg, sizeof(arg));
- if (ret)
- goto err_free;
-
- bo->base.kms = kms;
- bo->base.handle = arg.handle;
- bo->base.size = size;
- bo->base.pitch = pitch;
-
- *out = &bo->base;
-
- return 0;
-
-err_free:
- free(bo);
- return ret;
-}
-
-static int
-exynos_bo_get_prop(struct kms_bo *bo, unsigned key, unsigned *out)
-{
- switch (key) {
- default:
- return -EINVAL;
- }
-}
-
-static int
-exynos_bo_map(struct kms_bo *_bo, void **out)
-{
- struct exynos_bo *bo = (struct exynos_bo *)_bo;
- struct drm_mode_map_dumb arg;
- void *map = NULL;
- int ret;
-
- if (bo->base.ptr) {
- bo->map_count++;
- *out = bo->base.ptr;
- return 0;
- }
-
- memset(&arg, 0, sizeof(arg));
- arg.handle = bo->base.handle;
-
- ret = drmIoctl(bo->base.kms->fd, DRM_IOCTL_MODE_MAP_DUMB, &arg);
- if (ret)
- return ret;
-
- map = drm_mmap(0, bo->base.size, PROT_READ | PROT_WRITE, MAP_SHARED, bo->base.kms->fd, arg.offset);
- if (map == MAP_FAILED)
- return -errno;
-
- bo->base.ptr = map;
- bo->map_count++;
- *out = bo->base.ptr;
-
- return 0;
-}
-
-static int
-exynos_bo_unmap(struct kms_bo *_bo)
-{
- struct exynos_bo *bo = (struct exynos_bo *)_bo;
- bo->map_count--;
- return 0;
-}
-
-static int
-exynos_bo_destroy(struct kms_bo *_bo)
-{
- struct exynos_bo *bo = (struct exynos_bo *)_bo;
- struct drm_gem_close arg;
- int ret;
-
- if (bo->base.ptr) {
- /* XXX Sanity check map_count */
- munmap(bo->base.ptr, bo->base.size);
- bo->base.ptr = NULL;
- }
-
- memset(&arg, 0, sizeof(arg));
- arg.handle = bo->base.handle;
-
- ret = drmIoctl(bo->base.kms->fd, DRM_IOCTL_GEM_CLOSE, &arg);
- if (ret)
- return -errno;
-
- free(bo);
- return 0;
-}
-
-drm_private int
|
|
[-]
[+]
|
Deleted |
_service:tar_git:libdrm-2.4.110+git1.tar.bz2/upstream/libkms/intel.c
^
|
| @@ -1,236 +0,0 @@
-/**************************************************************************
- *
- * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- **************************************************************************/
-
-
-#include <errno.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include "internal.h"
-
-#include <sys/ioctl.h>
-#include "xf86drm.h"
-#include "libdrm_macros.h"
-
-#include "i915_drm.h"
-
-struct intel_bo
-{
- struct kms_bo base;
- unsigned map_count;
-};
-
-static int
-intel_get_prop(struct kms_driver *kms, unsigned key, unsigned *out)
-{
- switch (key) {
- case KMS_BO_TYPE:
- *out = KMS_BO_TYPE_SCANOUT_X8R8G8B8 | KMS_BO_TYPE_CURSOR_64X64_A8R8G8B8;
- break;
- default:
- return -EINVAL;
- }
- return 0;
-}
-
-static int
-intel_destroy(struct kms_driver *kms)
-{
- free(kms);
- return 0;
-}
-
-static int
-intel_bo_create(struct kms_driver *kms,
- const unsigned width, const unsigned height,
- const enum kms_bo_type type, const unsigned *attr,
- struct kms_bo **out)
-{
- struct drm_i915_gem_create arg;
- unsigned size, pitch;
- struct intel_bo *bo;
- int i, ret;
-
- for (i = 0; attr[i]; i += 2) {
- switch (attr[i]) {
- case KMS_WIDTH:
- case KMS_HEIGHT:
- case KMS_BO_TYPE:
- break;
- default:
- return -EINVAL;
- }
- }
-
- bo = calloc(1, sizeof(*bo));
- if (!bo)
- return -ENOMEM;
-
- if (type == KMS_BO_TYPE_CURSOR_64X64_A8R8G8B8) {
- pitch = 64 * 4;
- size = 64 * 64 * 4;
- } else if (type == KMS_BO_TYPE_SCANOUT_X8R8G8B8) {
- pitch = width * 4;
- pitch = (pitch + 512 - 1) & ~(512 - 1);
- size = pitch * ((height + 4 - 1) & ~(4 - 1));
- } else {
- free(bo);
- return -EINVAL;
- }
-
- memset(&arg, 0, sizeof(arg));
- arg.size = size;
-
- ret = drmCommandWriteRead(kms->fd, DRM_I915_GEM_CREATE, &arg, sizeof(arg));
- if (ret)
- goto err_free;
-
- bo->base.kms = kms;
- bo->base.handle = arg.handle;
- bo->base.size = size;
- bo->base.pitch = pitch;
-
- *out = &bo->base;
- if (type == KMS_BO_TYPE_SCANOUT_X8R8G8B8 && pitch > 512) {
- struct drm_i915_gem_set_tiling tile;
-
- memset(&tile, 0, sizeof(tile));
- tile.handle = bo->base.handle;
- tile.tiling_mode = I915_TILING_X;
- tile.stride = bo->base.pitch;
-
- ret = drmCommandWriteRead(kms->fd, DRM_I915_GEM_SET_TILING, &tile, sizeof(tile));
-#if 0
- if (ret) {
- kms_bo_destroy(out);
- return ret;
- }
-#endif
- }
-
- return 0;
-
-err_free:
- free(bo);
- return ret;
-}
-
-static int
-intel_bo_get_prop(struct kms_bo *bo, unsigned key, unsigned *out)
-{
- switch (key) {
- default:
- return -EINVAL;
- }
-}
-
-static int
-intel_bo_map(struct kms_bo *_bo, void **out)
-{
- struct intel_bo *bo = (struct intel_bo *)_bo;
- struct drm_i915_gem_mmap_gtt arg;
- void *map = NULL;
- int ret;
-
- if (bo->base.ptr) {
- bo->map_count++;
- *out = bo->base.ptr;
- return 0;
- }
-
- memset(&arg, 0, sizeof(arg));
- arg.handle = bo->base.handle;
-
- ret = drmCommandWriteRead(bo->base.kms->fd, DRM_I915_GEM_MMAP_GTT, &arg, sizeof(arg));
- if (ret)
- return ret;
-
- map = drm_mmap(0, bo->base.size, PROT_READ | PROT_WRITE, MAP_SHARED, bo->base.kms->fd, arg.offset);
- if (map == MAP_FAILED)
- return -errno;
-
- bo->base.ptr = map;
- bo->map_count++;
- *out = bo->base.ptr;
-
- return 0;
-}
-
-static int
-intel_bo_unmap(struct kms_bo *_bo)
-{
- struct intel_bo *bo = (struct intel_bo *)_bo;
- bo->map_count--;
- return 0;
-}
-
-static int
-intel_bo_destroy(struct kms_bo *_bo)
-{
- struct intel_bo *bo = (struct intel_bo *)_bo;
- struct drm_gem_close arg;
- int ret;
-
- if (bo->base.ptr) {
- /* XXX Sanity check map_count */
|
|
[-]
[+]
|
Deleted |
_service:tar_git:libdrm-2.4.110+git1.tar.bz2/upstream/libkms/internal.h
^
|
| @@ -1,80 +0,0 @@
-/**************************************************************************
- *
- * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- **************************************************************************/
-
-
-#ifndef INTERNAL_H_
-#define INTERNAL_H_
-
-#include "libdrm_macros.h"
-#include "libkms.h"
-
-struct kms_driver
-{
- int (*get_prop)(struct kms_driver *kms, const unsigned key,
- unsigned *out);
- int (*destroy)(struct kms_driver *kms);
-
- int (*bo_create)(struct kms_driver *kms,
- unsigned width,
- unsigned height,
- enum kms_bo_type type,
- const unsigned *attr,
- struct kms_bo **out);
- int (*bo_get_prop)(struct kms_bo *bo, const unsigned key,
- unsigned *out);
- int (*bo_map)(struct kms_bo *bo, void **out);
- int (*bo_unmap)(struct kms_bo *bo);
- int (*bo_destroy)(struct kms_bo *bo);
-
- int fd;
-};
-
-struct kms_bo
-{
- struct kms_driver *kms;
- void *ptr;
- size_t size;
- size_t offset;
- size_t pitch;
- unsigned handle;
-};
-
-drm_private int linux_create(int fd, struct kms_driver **out);
-
-drm_private int vmwgfx_create(int fd, struct kms_driver **out);
-
-drm_private int intel_create(int fd, struct kms_driver **out);
-
-drm_private int dumb_create(int fd, struct kms_driver **out);
-
-drm_private int nouveau_create(int fd, struct kms_driver **out);
-
-drm_private int radeon_create(int fd, struct kms_driver **out);
-
-drm_private int exynos_create(int fd, struct kms_driver **out);
-
-#endif
|
|
[-]
[+]
|
Deleted |
_service:tar_git:libdrm-2.4.110+git1.tar.bz2/upstream/libkms/kms-symbols.txt
^
|
| @@ -1,8 +0,0 @@
-kms_bo_create
-kms_bo_destroy
-kms_bo_get_prop
-kms_bo_map
-kms_bo_unmap
-kms_create
-kms_destroy
-kms_get_prop
|
|
[-]
[+]
|
Deleted |
_service:tar_git:libdrm-2.4.110+git1.tar.bz2/upstream/libkms/libkms.h
^
|
| @@ -1,82 +0,0 @@
-/**************************************************************************
- *
- * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- **************************************************************************/
-
-
-#ifndef _LIBKMS_H_
-#define _LIBKMS_H_
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/**
- * \file
- *
- */
-
-struct kms_driver;
-struct kms_bo;
-
-enum kms_attrib
-{
- KMS_TERMINATE_PROP_LIST,
-#define KMS_TERMINATE_PROP_LIST KMS_TERMINATE_PROP_LIST
- KMS_BO_TYPE,
-#define KMS_BO_TYPE KMS_BO_TYPE
- KMS_WIDTH,
-#define KMS_WIDTH KMS_WIDTH
- KMS_HEIGHT,
-#define KMS_HEIGHT KMS_HEIGHT
- KMS_PITCH,
-#define KMS_PITCH KMS_PITCH
- KMS_HANDLE,
-#define KMS_HANDLE KMS_HANDLE
-};
-
-enum kms_bo_type
-{
- KMS_BO_TYPE_SCANOUT_X8R8G8B8 = (1 << 0),
-#define KMS_BO_TYPE_SCANOUT_X8R8G8B8 KMS_BO_TYPE_SCANOUT_X8R8G8B8
- KMS_BO_TYPE_CURSOR_64X64_A8R8G8B8 = (1 << 1),
-#define KMS_BO_TYPE_CURSOR_64X64_A8R8G8B8 KMS_BO_TYPE_CURSOR_64X64_A8R8G8B8
-};
-
-int kms_create(int fd, struct kms_driver **out);
-int kms_get_prop(struct kms_driver *kms, unsigned key, unsigned *out);
-int kms_destroy(struct kms_driver **kms);
-
-int kms_bo_create(struct kms_driver *kms, const unsigned *attr, struct kms_bo **out);
-int kms_bo_get_prop(struct kms_bo *bo, unsigned key, unsigned *out);
-int kms_bo_map(struct kms_bo *bo, void **out);
-int kms_bo_unmap(struct kms_bo *bo);
-int kms_bo_destroy(struct kms_bo **bo);
-
-#if defined(__cplusplus)
-};
-#endif
-
-#endif
|
|
[-]
[+]
|
Deleted |
_service:tar_git:libdrm-2.4.110+git1.tar.bz2/upstream/libkms/libkms.pc.in
^
|
| @@ -1,11 +0,0 @@
-prefix=@prefix@
-exec_prefix=@exec_prefix@
-libdir=@libdir@
-includedir=@includedir@
-
-Name: libkms
-Description: Library that abstracts away the different mm interface for kernel drivers
-Version: 1.0.0
-Libs: -L${libdir} -lkms
-Cflags: -I${includedir}/libkms
-Requires.private: libdrm
|
|
[-]
[+]
|
Deleted |
_service:tar_git:libdrm-2.4.110+git1.tar.bz2/upstream/libkms/linux.c
^
|
| @@ -1,147 +0,0 @@
-/**************************************************************************
- *
- * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- **************************************************************************/
-/*
- * Thanks to krh and jcristau for the tips on
- * going from fd to pci id via fstat and udev.
- */
-
-#include <errno.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <xf86drm.h>
-#include <string.h>
-#include <unistd.h>
-#include <sys/stat.h>
-#include <sys/types.h>
-#ifdef MAJOR_IN_MKDEV
-#include <sys/mkdev.h>
-#endif
-#ifdef MAJOR_IN_SYSMACROS
-#include <sys/sysmacros.h>
-#endif
-
-#include "libdrm_macros.h"
-#include "internal.h"
-
-#define PATH_SIZE 512
-
-static int
-linux_name_from_sysfs(int fd, char **out)
-{
- char path[PATH_SIZE+1] = ""; /* initialize to please valgrind */
- char link[PATH_SIZE+1] = "";
- struct stat buffer;
- unsigned maj, min;
- char* slash_name;
- int ret;
-
- /*
- * Inside the sysfs directory for the device there is a symlink
- * to the directory representing the driver module, that path
- * happens to hold the name of the driver.
- *
- * So lets get the symlink for the drm device. Then read the link
- * and filter out the last directory which happens to be the name
- * of the driver, which we can use to load the correct interface.
- *
- * Thanks to Ray Strode of Plymouth for the code.
- */
-
- ret = fstat(fd, &buffer);
- if (ret)
- return -EINVAL;
-
- if (!S_ISCHR(buffer.st_mode))
- return -EINVAL;
-
- maj = major(buffer.st_rdev);
- min = minor(buffer.st_rdev);
-
- snprintf(path, PATH_SIZE, "/sys/dev/char/%d:%d/device/driver", maj, min);
-
- if (readlink(path, link, PATH_SIZE) < 0)
- return -EINVAL;
-
- /* link looks something like this: ../../../bus/pci/drivers/intel */
- slash_name = strrchr(link, '/');
- if (!slash_name)
- return -EINVAL;
-
- /* copy name and at the same time remove the slash */
- *out = strdup(slash_name + 1);
- return 0;
-}
-
-static int
-linux_from_sysfs(int fd, struct kms_driver **out)
-{
- char *name;
- int ret;
-
- ret = linux_name_from_sysfs(fd, &name);
- if (ret)
- return ret;
-
-#if HAVE_INTEL
- if (!strcmp(name, "intel"))
- ret = intel_create(fd, out);
- else
-#endif
-#if HAVE_VMWGFX
- if (!strcmp(name, "vmwgfx"))
- ret = vmwgfx_create(fd, out);
- else
-#endif
-#if HAVE_NOUVEAU
- if (!strcmp(name, "nouveau"))
- ret = nouveau_create(fd, out);
- else
-#endif
-#if HAVE_RADEON
- if (!strcmp(name, "radeon"))
- ret = radeon_create(fd, out);
- else
-#endif
-#if HAVE_EXYNOS
- if (!strcmp(name, "exynos"))
- ret = exynos_create(fd, out);
- else
-#endif
- ret = -ENOSYS;
-
- free(name);
- return ret;
-}
-
-drm_private int
-linux_create(int fd, struct kms_driver **out)
-{
- if (!dumb_create(fd, out))
- return 0;
-
- return linux_from_sysfs(fd, out);
-}
|
|
[-]
[+]
|
Deleted |
_service:tar_git:libdrm-2.4.110+git1.tar.bz2/upstream/libkms/meson.build
^
|
| @@ -1,81 +0,0 @@
-# Copyright © 2017-2018 Intel Corporation
-
-# Permission is hereby granted, free of charge, to any person obtaining a copy
-# of this software and associated documentation files (the "Software"), to deal
-# in the Software without restriction, including without limitation the rights
-# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-# copies of the Software, and to permit persons to whom the Software is
-# furnished to do so, subject to the following conditions:
-
-# The above copyright notice and this permission notice shall be included in
-# all copies or substantial portions of the Software.
-
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-# SOFTWARE.
-
-libkms_include = [inc_root, inc_drm]
-files_libkms = files(
- 'linux.c',
- 'dumb.c',
- 'api.c',
-)
-if with_vmwgfx
- files_libkms += files('vmwgfx.c')
-endif
-if with_intel
- files_libkms += files('intel.c')
-endif
-if with_nouveau
- files_libkms += files('nouveau.c')
-endif
-if with_radeon
- files_libkms += files('radeon.c')
-endif
-if with_exynos
- files_libkms += files('exynos.c')
- libkms_include += include_directories('../exynos')
-endif
-
-libkms = library(
- 'kms',
- [files_libkms, config_file],
- c_args : libdrm_c_args,
- include_directories : libkms_include,
- link_with : libdrm,
- version : '1.0.0',
- install : true,
-)
-
-ext_libkms = declare_dependency(
- link_with : [libdrm, libkms],
- include_directories : [libkms_include],
-)
-
-if meson.version().version_compare('>= 0.54.0')
- meson.override_dependency('kms', ext_libkms)
-endif
-
-install_headers('libkms.h', subdir : 'libkms')
-
-pkg.generate(
- libkms,
- name : 'libkms',
- subdirs : ['libkms'],
- version : '1.0.0',
- description : 'Library that abstracts away the different mm interfaces for kernel drivers',
-)
-
-test(
- 'kms-symbols-check',
- symbols_check,
- args : [
- '--lib', libkms,
- '--symbols-file', files('kms-symbols.txt'),
- '--nm', prog_nm.path(),
- ],
-)
|
|
[-]
[+]
|
Deleted |
_service:tar_git:libdrm-2.4.110+git1.tar.bz2/upstream/libkms/nouveau.c
^
|
| @@ -1,218 +0,0 @@
-/**************************************************************************
- *
- * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- **************************************************************************/
-
-
-#include <errno.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include "internal.h"
-
-#include <sys/ioctl.h>
-#include "xf86drm.h"
-#include "libdrm_macros.h"
-
-#include "nouveau_drm.h"
-
-struct nouveau_bo
-{
- struct kms_bo base;
- uint64_t map_handle;
- unsigned map_count;
-};
-
-static int
-nouveau_get_prop(struct kms_driver *kms, unsigned key, unsigned *out)
-{
- switch (key) {
- case KMS_BO_TYPE:
- *out = KMS_BO_TYPE_SCANOUT_X8R8G8B8 | KMS_BO_TYPE_CURSOR_64X64_A8R8G8B8;
- break;
- default:
- return -EINVAL;
- }
- return 0;
-}
-
-static int
-nouveau_destroy(struct kms_driver *kms)
-{
- free(kms);
- return 0;
-}
-
-static int
-nouveau_bo_create(struct kms_driver *kms,
- const unsigned width, const unsigned height,
- const enum kms_bo_type type, const unsigned *attr,
- struct kms_bo **out)
-{
- struct drm_nouveau_gem_new arg;
- unsigned size, pitch;
- struct nouveau_bo *bo;
- int i, ret;
-
- for (i = 0; attr[i]; i += 2) {
- switch (attr[i]) {
- case KMS_WIDTH:
- case KMS_HEIGHT:
- case KMS_BO_TYPE:
- break;
- default:
- return -EINVAL;
- }
- }
-
- bo = calloc(1, sizeof(*bo));
- if (!bo)
- return -ENOMEM;
-
- if (type == KMS_BO_TYPE_CURSOR_64X64_A8R8G8B8) {
- pitch = 64 * 4;
- size = 64 * 64 * 4;
- } else if (type == KMS_BO_TYPE_SCANOUT_X8R8G8B8) {
- pitch = width * 4;
- pitch = (pitch + 512 - 1) & ~(512 - 1);
- size = pitch * height;
- } else {
- free(bo);
- return -EINVAL;
- }
-
- memset(&arg, 0, sizeof(arg));
- arg.info.size = size;
- arg.info.domain = NOUVEAU_GEM_DOMAIN_MAPPABLE | NOUVEAU_GEM_DOMAIN_VRAM;
- arg.info.tile_mode = 0;
- arg.info.tile_flags = 0;
- arg.align = 512;
- arg.channel_hint = 0;
-
- ret = drmCommandWriteRead(kms->fd, DRM_NOUVEAU_GEM_NEW, &arg, sizeof(arg));
- if (ret)
- goto err_free;
-
- bo->base.kms = kms;
- bo->base.handle = arg.info.handle;
- bo->base.size = size;
- bo->base.pitch = pitch;
- bo->map_handle = arg.info.map_handle;
-
- *out = &bo->base;
-
- return 0;
-
-err_free:
- free(bo);
- return ret;
-}
-
-static int
-nouveau_bo_get_prop(struct kms_bo *bo, unsigned key, unsigned *out)
-{
- switch (key) {
- default:
- return -EINVAL;
- }
-}
-
-static int
-nouveau_bo_map(struct kms_bo *_bo, void **out)
-{
- struct nouveau_bo *bo = (struct nouveau_bo *)_bo;
- void *map = NULL;
-
- if (bo->base.ptr) {
- bo->map_count++;
- *out = bo->base.ptr;
- return 0;
- }
-
- map = drm_mmap(0, bo->base.size, PROT_READ | PROT_WRITE, MAP_SHARED, bo->base.kms->fd, bo->map_handle);
- if (map == MAP_FAILED)
- return -errno;
-
- bo->base.ptr = map;
- bo->map_count++;
- *out = bo->base.ptr;
-
- return 0;
-}
-
-static int
-nouveau_bo_unmap(struct kms_bo *_bo)
-{
- struct nouveau_bo *bo = (struct nouveau_bo *)_bo;
- bo->map_count--;
- return 0;
-}
-
-static int
-nouveau_bo_destroy(struct kms_bo *_bo)
-{
- struct nouveau_bo *bo = (struct nouveau_bo *)_bo;
- struct drm_gem_close arg;
- int ret;
-
- if (bo->base.ptr) {
- /* XXX Sanity check map_count */
- drm_munmap(bo->base.ptr, bo->base.size);
- bo->base.ptr = NULL;
- }
-
- memset(&arg, 0, sizeof(arg));
- arg.handle = bo->base.handle;
-
- ret = drmIoctl(bo->base.kms->fd, DRM_IOCTL_GEM_CLOSE, &arg);
- if (ret)
- return -errno;
-
- free(bo);
- return 0;
-}
-
-drm_private int
-nouveau_create(int fd, struct kms_driver **out)
-{
|
|
[-]
[+]
|
Deleted |
_service:tar_git:libdrm-2.4.110+git1.tar.bz2/upstream/libkms/radeon.c
^
|
| @@ -1,239 +0,0 @@
-/**************************************************************************
- *
- * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- **************************************************************************/
-
-
-#include <errno.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include "internal.h"
-
-#include <sys/ioctl.h>
-#include "xf86drm.h"
-#include "libdrm_macros.h"
-
-#include "radeon_drm.h"
-
-
-#define ALIGNMENT 512
-
-struct radeon_bo
-{
- struct kms_bo base;
- unsigned map_count;
-};
-
-static int
-radeon_get_prop(struct kms_driver *kms, unsigned key, unsigned *out)
-{
- switch (key) {
- case KMS_BO_TYPE:
- *out = KMS_BO_TYPE_SCANOUT_X8R8G8B8 | KMS_BO_TYPE_CURSOR_64X64_A8R8G8B8;
- break;
- default:
- return -EINVAL;
- }
- return 0;
-}
-
-static int
-radeon_destroy(struct kms_driver *kms)
-{
- free(kms);
- return 0;
-}
-
-static int
-radeon_bo_create(struct kms_driver *kms,
- const unsigned width, const unsigned height,
- const enum kms_bo_type type, const unsigned *attr,
- struct kms_bo **out)
-{
- struct drm_radeon_gem_create arg;
- unsigned size, pitch;
- struct radeon_bo *bo;
- int i, ret;
-
- for (i = 0; attr[i]; i += 2) {
- switch (attr[i]) {
- case KMS_WIDTH:
- case KMS_HEIGHT:
- case KMS_BO_TYPE:
- break;
- default:
- return -EINVAL;
- }
- }
-
- switch (type) {
- case KMS_BO_TYPE_CURSOR_64X64_A8R8G8B8:
- pitch = 4 * 64;
- size = 4 * 64 * 64;
- break;
- case KMS_BO_TYPE_SCANOUT_X8R8G8B8:
- pitch = width * 4;
- pitch = (pitch + ALIGNMENT - 1) & ~(ALIGNMENT - 1);
- size = pitch * height;
- break;
- default:
- return -EINVAL;
- }
-
- bo = calloc(1, sizeof(*bo));
- if (!bo)
- return -ENOMEM;
-
- memset(&arg, 0, sizeof(arg));
- arg.size = size;
- arg.alignment = ALIGNMENT;
- arg.initial_domain = RADEON_GEM_DOMAIN_CPU;
- arg.flags = 0;
- arg.handle = 0;
-
- ret = drmCommandWriteRead(kms->fd, DRM_RADEON_GEM_CREATE,
- &arg, sizeof(arg));
- if (ret)
- goto err_free;
-
- bo->base.kms = kms;
- bo->base.handle = arg.handle;
- bo->base.size = size;
- bo->base.pitch = pitch;
- bo->base.offset = 0;
- bo->map_count = 0;
-
- *out = &bo->base;
-
- return 0;
-
-err_free:
- free(bo);
- return ret;
-}
-
-static int
-radeon_bo_get_prop(struct kms_bo *bo, unsigned key, unsigned *out)
-{
- switch (key) {
- default:
- return -EINVAL;
- }
-}
-
-static int
-radeon_bo_map(struct kms_bo *_bo, void **out)
-{
- struct radeon_bo *bo = (struct radeon_bo *)_bo;
- struct drm_radeon_gem_mmap arg;
- void *map = NULL;
- int ret;
-
- if (bo->base.ptr) {
- bo->map_count++;
- *out = bo->base.ptr;
- return 0;
- }
-
- memset(&arg, 0, sizeof(arg));
- arg.handle = bo->base.handle;
- arg.offset = bo->base.offset;
- arg.size = (uint64_t)bo->base.size;
-
- ret = drmCommandWriteRead(bo->base.kms->fd, DRM_RADEON_GEM_MMAP,
- &arg, sizeof(arg));
- if (ret)
- return -errno;
-
- map = drm_mmap(0, arg.size, PROT_READ | PROT_WRITE, MAP_SHARED,
- bo->base.kms->fd, arg.addr_ptr);
- if (map == MAP_FAILED)
- return -errno;
-
- bo->base.ptr = map;
- bo->map_count++;
- *out = bo->base.ptr;
-
- return 0;
-}
-
-static int
-radeon_bo_unmap(struct kms_bo *_bo)
-{
- struct radeon_bo *bo = (struct radeon_bo *)_bo;
- if (--bo->map_count == 0) {
- drm_munmap(bo->base.ptr, bo->base.size);
- bo->base.ptr = NULL;
- }
- return 0;
-}
-
-static int
-radeon_bo_destroy(struct kms_bo *_bo)
-{
- struct radeon_bo *bo = (struct radeon_bo *)_bo;
- struct drm_gem_close arg;
- int ret;
|
|
[-]
[+]
|
Deleted |
_service:tar_git:libdrm-2.4.110+git1.tar.bz2/upstream/libkms/vmwgfx.c
^
|
| @@ -1,207 +0,0 @@
-/**************************************************************************
- *
- * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- **************************************************************************/
-
-#ifdef __FreeBSD__
-#define _WANT_KERNEL_ERRNO
-#endif
-
-#include <errno.h>
-#include <stdlib.h>
-#include <string.h>
-#include "internal.h"
-
-#include "xf86drm.h"
-#include "libdrm_macros.h"
-#include "vmwgfx_drm.h"
-
-struct vmwgfx_bo
-{
- struct kms_bo base;
- uint64_t map_handle;
- unsigned map_count;
-};
-
-static int
-vmwgfx_get_prop(struct kms_driver *kms, unsigned key, unsigned *out)
-{
- switch (key) {
- case KMS_BO_TYPE:
- *out = KMS_BO_TYPE_SCANOUT_X8R8G8B8 | KMS_BO_TYPE_CURSOR_64X64_A8R8G8B8;
- break;
- default:
- return -EINVAL;
- }
- return 0;
-}
-
-static int
-vmwgfx_destroy(struct kms_driver *kms)
-{
- free(kms);
- return 0;
-}
-
-static int
-vmwgfx_bo_create(struct kms_driver *kms,
- const unsigned width, const unsigned height,
- const enum kms_bo_type type, const unsigned *attr,
- struct kms_bo **out)
-{
- struct vmwgfx_bo *bo;
- int i, ret;
-
- for (i = 0; attr[i]; i += 2) {
- switch (attr[i]) {
- case KMS_WIDTH:
- case KMS_HEIGHT:
- case KMS_BO_TYPE:
- break;
- default:
- return -EINVAL;
- }
- }
-
- bo = calloc(1, sizeof(*bo));
- if (!bo)
- return -EINVAL;
-
- {
- union drm_vmw_alloc_dmabuf_arg arg;
- struct drm_vmw_alloc_dmabuf_req *req = &arg.req;
- struct drm_vmw_dmabuf_rep *rep = &arg.rep;
-
- memset(&arg, 0, sizeof(arg));
- req->size = width * height * 4;
- bo->base.size = req->size;
- bo->base.pitch = width * 4;
- bo->base.kms = kms;
-
- do {
- ret = drmCommandWriteRead(bo->base.kms->fd,
- DRM_VMW_ALLOC_DMABUF,
- &arg, sizeof(arg));
- } while (ret == -ERESTART);
-
- if (ret)
- goto err_free;
-
- bo->base.handle = rep->handle;
- bo->map_handle = rep->map_handle;
- bo->base.handle = rep->cur_gmr_id;
- bo->base.offset = rep->cur_gmr_offset;
- }
-
- *out = &bo->base;
-
- return 0;
-
-err_free:
- free(bo);
- return ret;
-}
-
-static int
-vmwgfx_bo_get_prop(struct kms_bo *bo, unsigned key, unsigned *out)
-{
- switch (key) {
- default:
- return -EINVAL;
- }
-}
-
-static int
-vmwgfx_bo_map(struct kms_bo *_bo, void **out)
-{
- struct vmwgfx_bo *bo = (struct vmwgfx_bo *)_bo;
- void *map;
-
- if (bo->base.ptr) {
- bo->map_count++;
- *out = bo->base.ptr;
- return 0;
- }
-
- map = drm_mmap(NULL, bo->base.size, PROT_READ | PROT_WRITE, MAP_SHARED, bo->base.kms->fd, bo->map_handle);
- if (map == MAP_FAILED)
- return -errno;
-
- bo->base.ptr = map;
- bo->map_count++;
- *out = bo->base.ptr;
-
- return 0;
-}
-
-static int
-vmwgfx_bo_unmap(struct kms_bo *_bo)
-{
- struct vmwgfx_bo *bo = (struct vmwgfx_bo *)_bo;
- bo->map_count--;
- return 0;
-}
-
-static int
-vmwgfx_bo_destroy(struct kms_bo *_bo)
-{
- struct vmwgfx_bo *bo = (struct vmwgfx_bo *)_bo;
- struct drm_vmw_unref_dmabuf_arg arg;
-
- if (bo->base.ptr) {
- /* XXX Sanity check map_count */
- drm_munmap(bo->base.ptr, bo->base.size);
- bo->base.ptr = NULL;
- }
-
- memset(&arg, 0, sizeof(arg));
- arg.handle = bo->base.handle;
- drmCommandWrite(bo->base.kms->fd, DRM_VMW_UNREF_DMABUF, &arg, sizeof(arg));
-
- free(bo);
- return 0;
-}
-
-drm_private int
-vmwgfx_create(int fd, struct kms_driver **out)
-{
- struct kms_driver *kms;
-
- kms = calloc(1, sizeof(*kms));
- if (!kms)
- return -ENOMEM;
-
- kms->fd = fd;
-
- kms->bo_create = vmwgfx_bo_create;
- kms->bo_map = vmwgfx_bo_map;
|
|
[-]
[+]
|
Deleted |
_service:tar_git:libdrm-2.4.110+git1.tar.bz2/upstream/tests/kms/kms-steal-crtc.c
^
|
| @@ -1,161 +0,0 @@
-/*
- * Copyright © 2014 NVIDIA Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-#include <errno.h>
-#include <fcntl.h>
-#include <signal.h>
-#include <stdio.h>
-#include <stdint.h>
-#include <string.h>
-#include <unistd.h>
-#if HAVE_SYS_SELECT_H
-#include <sys/select.h>
-#endif
-
-#include <drm_fourcc.h>
-
-#include "util/pattern.h"
-#include "libkms-test.h"
-
-static void signal_handler(int signum)
-{
-}
-
-int main(int argc, char *argv[])
-{
- struct kms_framebuffer *fb;
- struct kms_screen *screen;
- struct kms_device *device;
- unsigned int index = 0;
- struct sigaction sa;
- int fd, err;
- void *ptr;
-
- if (argc < 2) {
- fprintf(stderr, "usage: %s DEVICE\n", argv[0]);
- return 1;
- }
-
- memset(&sa, 0, sizeof(sa));
- sa.sa_handler = signal_handler;
-
- err = sigaction(SIGINT, &sa, NULL);
- if (err < 0) {
- fprintf(stderr, "sigaction() failed: %m\n");
- return 1;
- }
-
- fd = open(argv[1], O_RDWR);
- if (fd < 0) {
- fprintf(stderr, "open() failed: %m\n");
- return 1;
- }
-
- device = kms_device_open(fd);
- if (!device) {
- fprintf(stderr, "kms_device_open() failed: %m\n");
- return 1;
- }
-
- if (device->num_screens < 1) {
- fprintf(stderr, "no screens found\n");
- kms_device_close(device);
- close(fd);
- return 1;
- }
-
- /* TODO: allow command-line to override */
- screen = device->screens[0];
-
- printf("Using screen %s, resolution %ux%u\n", screen->name,
- screen->width, screen->height);
-
- fb = kms_framebuffer_create(device, screen->width, screen->height,
- DRM_FORMAT_XRGB8888);
- if (!fb) {
- fprintf(stderr, "kms_framebuffer_create() failed\n");
- return 1;
- }
-
- err = kms_framebuffer_map(fb, &ptr);
- if (err < 0) {
- fprintf(stderr, "kms_framebuffer_map() failed: %d\n", err);
- return 1;
- }
-
- util_fill_pattern(fb->format, UTIL_PATTERN_SMPTE, &ptr, fb->width,
- fb->height, fb->pitch);
-
- kms_framebuffer_unmap(fb);
-
- err = kms_screen_set(screen, device->crtcs[index++], fb);
- if (err < 0) {
- fprintf(stderr, "kms_screen_set() failed: %d\n", err);
- return 1;
- }
-
- while (true) {
- int nfds = STDIN_FILENO + 1;
- struct timeval timeout;
- fd_set fds;
-
- memset(&timeout, 0, sizeof(timeout));
- timeout.tv_sec = 5;
- timeout.tv_usec = 0;
-
- FD_ZERO(&fds);
- FD_SET(STDIN_FILENO, &fds);
-
- err = select(nfds, &fds, NULL, NULL, &timeout);
- if (err < 0) {
- if (errno == EINTR)
- break;
-
- fprintf(stderr, "select() failed: %d\n", errno);
- break;
- }
-
- if (err > 0) {
- if (FD_ISSET(STDIN_FILENO, &fds))
- break;
- }
-
- /* switch CRTC */
- if (index >= device->num_crtcs)
- index = 0;
-
- err = kms_screen_set(screen, device->crtcs[index], fb);
- if (err < 0) {
- fprintf(stderr, "kms_screen_set() failed: %d\n", err);
- break;
- }
-
- index++;
- }
-
- kms_framebuffer_free(fb);
- kms_device_close(device);
- close(fd);
-
- return 0;
-}
|
|
[-]
[+]
|
Deleted |
_service:tar_git:libdrm-2.4.110+git1.tar.bz2/upstream/tests/kms/kms-universal-planes.c
^
|
| @@ -1,357 +0,0 @@
-/*
- * Copyright © 2014 NVIDIA Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-#include <fcntl.h>
-#include <getopt.h>
-#include <stdbool.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <string.h>
-#include <unistd.h>
-#if HAVE_SYS_SELECT_H
-#include <sys/select.h>
-#endif
-
-#include <drm_fourcc.h>
-#include "xf86drm.h"
-
-#include "util/common.h"
-#include "libkms-test.h"
-
-static const uint32_t formats[] = {
- DRM_FORMAT_XRGB8888,
- DRM_FORMAT_XBGR8888,
- DRM_FORMAT_RGBA8888,
-};
-
-static uint32_t choose_format(struct kms_plane *plane)
-{
- unsigned int i;
-
- for (i = 0; i < ARRAY_SIZE(formats); i++)
- if (kms_plane_supports_format(plane, formats[i]))
- return formats[i];
-
- return 0;
-}
-
-static void prepare_framebuffer(struct kms_framebuffer *fb, bool invert)
-{
- const unsigned int block_size = 16;
- uint32_t colors[2];
- unsigned int i, j;
- uint32_t *buf;
- void *ptr;
- int err;
-
- switch (fb->format) {
- case DRM_FORMAT_XRGB8888:
- printf("using XRGB8888 format\n");
- /* XXRRGGBB */
- colors[0] = 0xffff0000;
- colors[1] = 0xff0000ff;
- break;
-
- case DRM_FORMAT_XBGR8888:
- printf("using XBGR8888 format\n");
- /* XXBBGGRR */
- colors[0] = 0xff0000ff;
- colors[1] = 0xffff0000;
- break;
-
- case DRM_FORMAT_RGBA8888:
- printf("using RGBA8888 format\n");
- /* RRGGBBAA */
- colors[0] = 0xff0000ff;
- colors[1] = 0x0000ffff;
- break;
-
- default:
- colors[0] = 0xffffffff;
- colors[1] = 0xffffffff;
- break;
- }
-
- err = kms_framebuffer_map(fb, &ptr);
- if (err < 0) {
- fprintf(stderr, "kms_framebuffer_map() failed: %s\n",
- strerror(-err));
- return;
- }
-
- buf = ptr;
-
- for (j = 0; j < fb->height; j++) {
- for (i = 0; i < fb->width; i++) {
- unsigned int color = (j / block_size) ^
- (i / block_size);
-
- if (invert)
- color ^= color;
-
- *buf++ = colors[color & 1];
- }
- }
-
- kms_framebuffer_unmap(fb);
-}
-
-int main(int argc, char *argv[])
-{
- static const char opts[] = "chopv";
- static struct option options[] = {
- { "cursor", 0, 0, 'c' },
- { "help", 0, 0, 'h' },
- { "overlay", 0, 0, 'o' },
- { "primary", 0, 0, 'p' },
- { "verbose", 0, 0, 'v' },
- { 0, 0, 0, 0 },
- };
- struct kms_framebuffer *cursor = NULL;
- struct kms_framebuffer *root = NULL;
- struct kms_framebuffer *fb = NULL;
- struct kms_device *device;
- bool use_overlay = false;
- bool use_primary = false;
- struct kms_plane *plane;
- bool use_cursor = false;
- bool verbose = false;
- unsigned int i;
- int opt, idx;
- int fd, err;
-
- while ((opt = getopt_long(argc, argv, opts, options, &idx)) != -1) {
- switch (opt) {
- case 'c':
- use_cursor = true;
- break;
-
- case 'h':
- break;
-
- case 'o':
- use_overlay = true;
- break;
-
- case 'p':
- use_primary = true;
- break;
-
- case 'v':
- verbose = true;
- break;
-
- default:
- printf("unknown option \"%c\"\n", opt);
- return 1;
- }
- }
-
- if (optind >= argc) {
- fprintf(stderr, "usage: %s [options] DEVICE\n", argv[0]);
- return 1;
- }
-
- fd = open(argv[optind], O_RDWR);
- if (fd < 0) {
- fprintf(stderr, "open() failed: %m\n");
- return 1;
- }
-
- err = drmSetClientCap(fd, DRM_CLIENT_CAP_UNIVERSAL_PLANES, 1);
- if (err < 0) {
- fprintf(stderr, "drmSetClientCap() failed: %d\n", err);
- return 1;
- }
-
- device = kms_device_open(fd);
- if (!device)
- return 1;
-
- if (verbose) {
- printf("Screens: %u\n", device->num_screens);
-
- for (i = 0; i < device->num_screens; i++) {
- struct kms_screen *screen = device->screens[i];
- const char *status = "disconnected";
-
- if (screen->connected)
- status = "connected";
|
|
[-]
[+]
|
Deleted |
_service:tar_git:libdrm-2.4.110+git1.tar.bz2/upstream/tests/kms/libkms-test-crtc.c
^
|
| @@ -1,43 +0,0 @@
-/*
- * Copyright © 2014 NVIDIA Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-#include "libkms-test.h"
-
-struct kms_crtc *kms_crtc_create(struct kms_device *device, uint32_t id)
-{
- struct kms_crtc *crtc;
-
- crtc = calloc(1, sizeof(*crtc));
- if (!crtc)
- return NULL;
-
- crtc->device = device;
- crtc->id = id;
-
- return crtc;
-}
-
-void kms_crtc_free(struct kms_crtc *crtc)
-{
- free(crtc);
-}
|
|
[-]
[+]
|
Deleted |
_service:tar_git:libdrm-2.4.110+git1.tar.bz2/upstream/tests/kms/libkms-test-device.c
^
|
| @@ -1,217 +0,0 @@
-/*
- * Copyright © 2014 NVIDIA Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-#include <stdio.h>
-#include <string.h>
-#include <unistd.h>
-
-#include "util/common.h"
-#include "libkms-test.h"
-
-static const char *const connector_names[] = {
- "Unknown",
- "VGA",
- "DVI-I",
- "DVI-D",
- "DVI-A",
- "Composite",
- "SVIDEO",
- "LVDS",
- "Component",
- "9PinDIN",
- "DisplayPort",
- "HDMI-A",
- "HDMI-B",
- "TV",
- "eDP",
- "Virtual",
- "DSI",
-};
-
-static void kms_device_probe_screens(struct kms_device *device)
-{
- unsigned int counts[ARRAY_SIZE(connector_names)];
- struct kms_screen *screen;
- drmModeRes *res;
- int i;
-
- memset(counts, 0, sizeof(counts));
-
- res = drmModeGetResources(device->fd);
- if (!res)
- return;
-
- device->screens = calloc(res->count_connectors, sizeof(screen));
- if (!device->screens)
- goto err_free_resources;
-
- for (i = 0; i < res->count_connectors; i++) {
- unsigned int *count;
- const char *type;
- int len;
-
- screen = kms_screen_create(device, res->connectors[i]);
- if (!screen)
- continue;
-
- /* assign a unique name to this screen */
- type = connector_names[screen->type];
- count = &counts[screen->type];
-
- len = snprintf(NULL, 0, "%s-%u", type, *count);
-
- screen->name = malloc(len + 1);
- if (!screen->name) {
- free(screen);
- continue;
- }
-
- snprintf(screen->name, len + 1, "%s-%u", type, *count);
- (*count)++;
-
- device->screens[i] = screen;
- device->num_screens++;
- }
-
-err_free_resources:
- drmModeFreeResources(res);
-}
-
-static void kms_device_probe_crtcs(struct kms_device *device)
-{
- struct kms_crtc *crtc;
- drmModeRes *res;
- int i;
-
- res = drmModeGetResources(device->fd);
- if (!res)
- return;
-
- device->crtcs = calloc(res->count_crtcs, sizeof(crtc));
- if (!device->crtcs)
- goto err_free_resources;
-
- for (i = 0; i < res->count_crtcs; i++) {
- crtc = kms_crtc_create(device, res->crtcs[i]);
- if (!crtc)
- continue;
-
- device->crtcs[i] = crtc;
- device->num_crtcs++;
- }
-
-err_free_resources:
- drmModeFreeResources(res);
-}
-
-static void kms_device_probe_planes(struct kms_device *device)
-{
- struct kms_plane *plane;
- drmModePlaneRes *res;
- unsigned int i;
-
- res = drmModeGetPlaneResources(device->fd);
- if (!res)
- return;
-
- device->planes = calloc(res->count_planes, sizeof(plane));
- if (!device->planes)
- goto err_free_resources;
-
- for (i = 0; i < res->count_planes; i++) {
- plane = kms_plane_create(device, res->planes[i]);
- if (!plane)
- continue;
-
- device->planes[i] = plane;
- device->num_planes++;
- }
-
-err_free_resources:
- drmModeFreePlaneResources(res);
-}
-
-static void kms_device_probe(struct kms_device *device)
-{
- kms_device_probe_screens(device);
- kms_device_probe_crtcs(device);
- kms_device_probe_planes(device);
-}
-
-struct kms_device *kms_device_open(int fd)
-{
- struct kms_device *device;
-
- device = calloc(1, sizeof(*device));
- if (!device)
- return NULL;
-
- device->fd = fd;
-
- kms_device_probe(device);
-
- return device;
-}
-
-void kms_device_close(struct kms_device *device)
-{
- unsigned int i;
-
- for (i = 0; i < device->num_planes; i++)
- kms_plane_free(device->planes[i]);
-
- free(device->planes);
-
- for (i = 0; i < device->num_crtcs; i++)
- kms_crtc_free(device->crtcs[i]);
-
- free(device->crtcs);
-
- for (i = 0; i < device->num_screens; i++)
- kms_screen_free(device->screens[i]);
-
- free(device->screens);
-
- if (device->fd >= 0)
- close(device->fd);
-
- free(device);
-}
|
|
[-]
[+]
|
Deleted |
_service:tar_git:libdrm-2.4.110+git1.tar.bz2/upstream/tests/kms/libkms-test-framebuffer.c
^
|
| @@ -1,153 +0,0 @@
-/*
- * Copyright © 2014 NVIDIA Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-#include <errno.h>
-#include <string.h>
-
-#include <sys/mman.h>
-
-#include <drm_fourcc.h>
-
-#include "xf86drm.h"
-
-#include "libkms-test.h"
-
-struct kms_framebuffer *kms_framebuffer_create(struct kms_device *device,
- unsigned int width,
- unsigned int height,
- uint32_t format)
-{
- uint32_t handles[4], pitches[4], offsets[4];
- struct drm_mode_create_dumb args;
- struct kms_framebuffer *fb;
- int err;
-
- fb = calloc(1, sizeof(*fb));
- if (!fb)
- return NULL;
-
- fb->device = device;
- fb->width = width;
- fb->height = height;
- fb->format = format;
-
- memset(&args, 0, sizeof(args));
- args.width = width;
- args.height = height;
-
- switch (format) {
- case DRM_FORMAT_XRGB8888:
- case DRM_FORMAT_XBGR8888:
- case DRM_FORMAT_RGBA8888:
- args.bpp = 32;
- break;
-
- default:
- free(fb);
- return NULL;
- }
-
- err = drmIoctl(device->fd, DRM_IOCTL_MODE_CREATE_DUMB, &args);
- if (err < 0) {
- free(fb);
- return NULL;
- }
-
- fb->handle = args.handle;
- fb->pitch = args.pitch;
- fb->size = args.size;
-
- handles[0] = fb->handle;
- pitches[0] = fb->pitch;
- offsets[0] = 0;
-
- err = drmModeAddFB2(device->fd, width, height, format, handles,
- pitches, offsets, &fb->id, 0);
- if (err < 0) {
- kms_framebuffer_free(fb);
- return NULL;
- }
-
- return fb;
-}
-
-void kms_framebuffer_free(struct kms_framebuffer *fb)
-{
- struct kms_device *device = fb->device;
- struct drm_mode_destroy_dumb args;
- int err;
-
- if (fb->id) {
- err = drmModeRmFB(device->fd, fb->id);
- if (err < 0) {
- /* not much we can do now */
- }
- }
-
- memset(&args, 0, sizeof(args));
- args.handle = fb->handle;
-
- err = drmIoctl(device->fd, DRM_IOCTL_MODE_DESTROY_DUMB, &args);
- if (err < 0) {
- /* not much we can do now */
- }
-
- free(fb);
-}
-
-int kms_framebuffer_map(struct kms_framebuffer *fb, void **ptrp)
-{
- struct kms_device *device = fb->device;
- struct drm_mode_map_dumb args;
- void *ptr;
- int err;
-
- if (fb->ptr) {
- *ptrp = fb->ptr;
- return 0;
- }
-
- memset(&args, 0, sizeof(args));
- args.handle = fb->handle;
-
- err = drmIoctl(device->fd, DRM_IOCTL_MODE_MAP_DUMB, &args);
- if (err < 0)
- return -errno;
-
- ptr = mmap(0, fb->size, PROT_READ | PROT_WRITE, MAP_SHARED,
- device->fd, args.offset);
- if (ptr == MAP_FAILED)
- return -errno;
-
- *ptrp = fb->ptr = ptr;
-
- return 0;
-}
-
-void kms_framebuffer_unmap(struct kms_framebuffer *fb)
-{
- if (fb->ptr) {
- munmap(fb->ptr, fb->size);
- fb->ptr = NULL;
- }
-}
|
|
[-]
[+]
|
Deleted |
_service:tar_git:libdrm-2.4.110+git1.tar.bz2/upstream/tests/kms/libkms-test-plane.c
^
|
| @@ -1,137 +0,0 @@
-/*
- * Copyright © 2014 NVIDIA Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-#include <errno.h>
-#include <string.h>
-
-#include "libkms-test.h"
-
-static int kms_plane_probe(struct kms_plane *plane)
-{
- struct kms_device *device = plane->device;
- drmModeObjectPropertiesPtr props;
- drmModePlane *p;
- unsigned int i;
-
- p = drmModeGetPlane(device->fd, plane->id);
- if (!p)
- return -ENODEV;
-
- /* TODO: allow dynamic assignment to CRTCs */
- if (p->crtc_id == 0) {
- for (i = 0; i < device->num_crtcs; i++) {
- if (p->possible_crtcs & (1 << i)) {
- p->crtc_id = device->crtcs[i]->id;
- break;
- }
- }
- }
-
- for (i = 0; i < device->num_crtcs; i++) {
- if (device->crtcs[i]->id == p->crtc_id) {
- plane->crtc = device->crtcs[i];
- break;
- }
- }
-
- plane->formats = calloc(p->count_formats, sizeof(uint32_t));
- if (!plane->formats) {
- drmModeFreePlane(p);
- return -ENOMEM;
- }
-
- for (i = 0; i < p->count_formats; i++)
- plane->formats[i] = p->formats[i];
-
- plane->num_formats = p->count_formats;
-
- drmModeFreePlane(p);
-
- props = drmModeObjectGetProperties(device->fd, plane->id,
- DRM_MODE_OBJECT_PLANE);
- if (!props)
- return -ENODEV;
-
- for (i = 0; i < props->count_props; i++) {
- drmModePropertyPtr prop;
-
- prop = drmModeGetProperty(device->fd, props->props[i]);
- if (prop) {
- if (strcmp(prop->name, "type") == 0)
- plane->type = props->prop_values[i];
-
- drmModeFreeProperty(prop);
- }
- }
-
- drmModeFreeObjectProperties(props);
-
- return 0;
-}
-
-struct kms_plane *kms_plane_create(struct kms_device *device, uint32_t id)
-{
- struct kms_plane *plane;
-
- plane = calloc(1, sizeof(*plane));
- if (!plane)
- return NULL;
-
- plane->device = device;
- plane->id = id;
-
- kms_plane_probe(plane);
-
- return plane;
-}
-
-void kms_plane_free(struct kms_plane *plane)
-{
- free(plane);
-}
-
-int kms_plane_set(struct kms_plane *plane, struct kms_framebuffer *fb,
- unsigned int x, unsigned int y)
-{
- struct kms_device *device = plane->device;
- int err;
-
- err = drmModeSetPlane(device->fd, plane->id, plane->crtc->id, fb->id,
- 0, x, y, fb->width, fb->height, 0 << 16,
- 0 << 16, fb->width << 16, fb->height << 16);
- if (err < 0)
- return -errno;
-
- return 0;
-}
-
-bool kms_plane_supports_format(struct kms_plane *plane, uint32_t format)
-{
- unsigned int i;
-
- for (i = 0; i < plane->num_formats; i++)
- if (plane->formats[i] == format)
- return true;
-
- return false;
-}
|
|
[-]
[+]
|
Deleted |
_service:tar_git:libdrm-2.4.110+git1.tar.bz2/upstream/tests/kms/libkms-test-screen.c
^
|
| @@ -1,90 +0,0 @@
-/*
- * Copyright © 2014 NVIDIA Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-#include <errno.h>
-#include <string.h>
-
-#include "libkms-test.h"
-
-static void kms_screen_probe(struct kms_screen *screen)
-{
- struct kms_device *device = screen->device;
- drmModeConnector *con;
-
- con = drmModeGetConnector(device->fd, screen->id);
- if (!con)
- return;
-
- screen->type = con->connector_type;
-
- if (con->connection == DRM_MODE_CONNECTED)
- screen->connected = true;
- else
- screen->connected = false;
-
- if (con->modes)
- memcpy(&screen->mode, &con->modes[0], sizeof(drmModeModeInfo));
-
- screen->width = screen->mode.hdisplay;
- screen->height = screen->mode.vdisplay;
-
- drmModeFreeConnector(con);
-}
-
-struct kms_screen *kms_screen_create(struct kms_device *device, uint32_t id)
-{
- struct kms_screen *screen;
-
- screen = calloc(1, sizeof(*screen));
- if (!screen)
- return NULL;
-
- screen->device = device;
- screen->id = id;
-
- kms_screen_probe(screen);
-
- return screen;
-}
-
-void kms_screen_free(struct kms_screen *screen)
-{
- if (screen)
- free(screen->name);
-
- free(screen);
-}
-
-int kms_screen_set(struct kms_screen *screen, struct kms_crtc *crtc,
- struct kms_framebuffer *fb)
-{
- struct kms_device *device = screen->device;
- int err;
-
- err = drmModeSetCrtc(device->fd, crtc->id, fb->id, 0, 0, &screen->id,
- 1, &screen->mode);
- if (err < 0)
- return -errno;
-
- return 0;
-}
|
|
[-]
[+]
|
Deleted |
_service:tar_git:libdrm-2.4.110+git1.tar.bz2/upstream/tests/kms/libkms-test.h
^
|
| @@ -1,120 +0,0 @@
-/*
- * Copyright © 2014 NVIDIA Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-#ifndef LIBKMS_TEST_H
-#define LIBKMS_TEST_H
-
-#include <stdbool.h>
-#include <stdint.h>
-#include <stdlib.h>
-
-#include <xf86drmMode.h>
-
-struct kms_device {
- int fd;
-
- struct kms_screen **screens;
- unsigned int num_screens;
-
- struct kms_crtc **crtcs;
- unsigned int num_crtcs;
-
- struct kms_plane **planes;
- unsigned int num_planes;
-};
-
-struct kms_device *kms_device_open(int fd);
-void kms_device_close(struct kms_device *device);
-
-struct kms_plane *kms_device_find_plane_by_type(struct kms_device *device,
- uint32_t type,
- unsigned int index);
-
-struct kms_crtc {
- struct kms_device *device;
- uint32_t id;
-};
-
-struct kms_crtc *kms_crtc_create(struct kms_device *device, uint32_t id);
-void kms_crtc_free(struct kms_crtc *crtc);
-
-struct kms_framebuffer {
- struct kms_device *device;
-
- unsigned int width;
- unsigned int height;
- unsigned int pitch;
- uint32_t format;
- size_t size;
-
- uint32_t handle;
- uint32_t id;
-
- void *ptr;
-};
-
-struct kms_framebuffer *kms_framebuffer_create(struct kms_device *device,
- unsigned int width,
- unsigned int height,
- uint32_t format);
-void kms_framebuffer_free(struct kms_framebuffer *fb);
-int kms_framebuffer_map(struct kms_framebuffer *fb, void **ptrp);
-void kms_framebuffer_unmap(struct kms_framebuffer *fb);
-
-struct kms_screen {
- struct kms_device *device;
- bool connected;
- uint32_t type;
- uint32_t id;
-
- unsigned int width;
- unsigned int height;
- char *name;
-
- drmModeModeInfo mode;
-};
-
-struct kms_screen *kms_screen_create(struct kms_device *device, uint32_t id);
-void kms_screen_free(struct kms_screen *screen);
-
-int kms_screen_set(struct kms_screen *screen, struct kms_crtc *crtc,
- struct kms_framebuffer *fb);
-
-struct kms_plane {
- struct kms_device *device;
- struct kms_crtc *crtc;
- unsigned int type;
- uint32_t id;
-
- uint32_t *formats;
- unsigned int num_formats;
-};
-
-struct kms_plane *kms_plane_create(struct kms_device *device, uint32_t id);
-void kms_plane_free(struct kms_plane *plane);
-
-int kms_plane_set(struct kms_plane *plane, struct kms_framebuffer *fb,
- unsigned int x, unsigned int y);
-bool kms_plane_supports_format(struct kms_plane *plane, uint32_t format);
-
-#endif
|
|
[-]
[+]
|
Deleted |
_service:tar_git:libdrm-2.4.110+git1.tar.bz2/upstream/tests/kms/meson.build
^
|
| @@ -1,49 +0,0 @@
-# Copyright © 2017-2018 Intel Corporation
-
-# Permission is hereby granted, free of charge, to any person obtaining a copy
-# of this software and associated documentation files (the "Software"), to deal
-# in the Software without restriction, including without limitation the rights
-# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-# copies of the Software, and to permit persons to whom the Software is
-# furnished to do so, subject to the following conditions:
-
-# The above copyright notice and this permission notice shall be included in
-# all copies or substantial portions of the Software.
-
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-# SOFTWARE.
-
-
-libkms_test = static_library(
- 'kms-test',
- files(
- 'libkms-test-crtc.c', 'libkms-test-device.c', 'libkms-test-framebuffer.c',
- 'libkms-test-plane.c', 'libkms-test-screen.c',
- ),
- include_directories : [inc_root, inc_tests, inc_drm],
- link_with : libdrm,
- c_args : libdrm_c_args,
-)
-
-kms_steal_crtc = executable(
- 'kms-steal-crtc',
- files('kms-steal-crtc.c'),
- dependencies : dep_cairo,
- include_directories : [inc_root, inc_tests, inc_drm],
- link_with : [libkms_test, libutil],
- install : with_install_tests,
-)
-
-kms_universal_planes = executable(
- 'kms-universal-planes',
- files('kms-universal-planes.c'),
- dependencies : dep_cairo,
- include_directories : [inc_root, inc_tests, inc_drm],
- link_with : [libkms_test],
- install : with_install_tests,
-)
|
|
[-]
[+]
|
Deleted |
_service:tar_git:libdrm-2.4.110+git1.tar.bz2/upstream/tests/kmstest/main.c
^
|
| @@ -1,109 +0,0 @@
-/**************************************************************************
- *
- * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- **************************************************************************/
-
-#include <getopt.h>
-#include <stdio.h>
-#include <string.h>
-#include "xf86drm.h"
-#include "libkms.h"
-
-#include "util/kms.h"
-
-#define CHECK_RET_RETURN(ret, str) \
- if (ret < 0) { \
- printf("%s: %s (%s)\n", __func__, str, strerror(-ret)); \
- return ret; \
- }
-
-static int test_bo(struct kms_driver *kms)
-{
- struct kms_bo *bo;
- int ret;
- unsigned attrs[7] = {
- KMS_WIDTH, 1024,
- KMS_HEIGHT, 768,
- KMS_BO_TYPE, KMS_BO_TYPE_SCANOUT_X8R8G8B8,
- KMS_TERMINATE_PROP_LIST,
- };
-
- ret = kms_bo_create(kms, attrs, &bo);
- CHECK_RET_RETURN(ret, "Could not create bo");
-
- kms_bo_destroy(&bo);
-
- return 0;
-}
-
-static void usage(const char *program)
-{
- fprintf(stderr, "Usage: %s [options]\n", program);
- fprintf(stderr, "\n");
- fprintf(stderr, " -D DEVICE open the given device\n");
- fprintf(stderr, " -M MODULE open the given module\n");
-}
-
-int main(int argc, char** argv)
-{
- static const char optstr[] = "D:M:";
- struct kms_driver *kms;
- int c, fd, ret;
- char *device = NULL;
- char *module = NULL;
-
- while ((c = getopt(argc, argv, optstr)) != -1) {
- switch (c) {
- case 'D':
- device = optarg;
- break;
- case 'M':
- module = optarg;
- break;
- default:
- usage(argv[0]);
- return 0;
- }
- }
-
- fd = util_open(device, module);
- CHECK_RET_RETURN(fd, "Could not open device");
-
- ret = kms_create(fd, &kms);
- CHECK_RET_RETURN(ret, "Failed to create kms driver");
-
- ret = test_bo(kms);
- if (ret)
- goto err;
-
- printf("%s: All ok!\n", __func__);
-
- kms_destroy(&kms);
- return 0;
-
-err:
- kms_destroy(&kms);
- return ret;
-}
|
|
[-]
[+]
|
Deleted |
_service:tar_git:libdrm-2.4.110+git1.tar.bz2/upstream/tests/kmstest/meson.build
^
|
| @@ -1,30 +0,0 @@
-# Copyright © 2017 Intel Corporation
-
-# Permission is hereby granted, free of charge, to any person obtaining a copy
-# of this software and associated documentation files (the "Software"), to deal
-# in the Software without restriction, including without limitation the rights
-# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-# copies of the Software, and to permit persons to whom the Software is
-# furnished to do so, subject to the following conditions:
-
-# The above copyright notice and this permission notice shall be included in
-# all copies or substantial portions of the Software.
-
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-# SOFTWARE.
-
-kmstest = executable(
- 'kmstest',
- files('main.c'),
- c_args : libdrm_c_args,
- include_directories : [
- inc_root, inc_tests, include_directories('../../libkms'), inc_drm,
- ],
- link_with : [libutil, libkms, libdrm],
- install : with_install_tests,
-)
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/.gitlab-ci.yml
^
|
| @@ -44,7 +44,7 @@
FDO_DISTRIBUTION_EXEC: 'pip3 install meson==0.53.0'
# bump this tag every time you change something which requires rebuilding the
# base image
- FDO_DISTRIBUTION_TAG: "2022-01-19.0"
+ FDO_DISTRIBUTION_TAG: "2022-08-22.0"
.debian-x86_64:
extends:
@@ -68,10 +68,10 @@
variables:
BUILD_OS: freebsd
FDO_DISTRIBUTION_VERSION: "13.0"
- FDO_DISTRIBUTION_PACKAGES: 'meson ninja pkgconf libpciaccess libpthread-stubs py38-docutils cairo'
+ FDO_DISTRIBUTION_PACKAGES: 'meson ninja pkgconf libpciaccess libpthread-stubs py39-docutils cairo'
# bump this tag every time you change something which requires rebuilding the
# base image
- FDO_DISTRIBUTION_TAG: "2021-11-10.1"
+ FDO_DISTRIBUTION_TAG: "2022-08-22.0"
.freebsd-x86_64:
extends:
@@ -191,23 +191,8 @@
GIT_DEPTH: 10
script:
- meson build
- -D amdgpu=true
- -D cairo-tests=true
- -D etnaviv=true
- -D exynos=true
- -D freedreno=true
- -D freedreno-kgsl=true
- -D intel=true
- -D libkms=true
- -D man-pages=true
- -D nouveau=true
- -D omap=true
- -D radeon=true
- -D tegra=true
+ --auto-features=enabled
-D udev=true
- -D valgrind=auto
- -D vc4=true
- -D vmwgfx=true
- ninja -C build
- ninja -C build test
- DESTDIR=$PWD/install ninja -C build install
@@ -228,7 +213,7 @@
# the workspace to see details about the failed tests.
- |
set +e
- /app/vmctl exec "pkg info; cd $CI_PROJECT_NAME ; meson build -D amdgpu=true -D cairo-tests=true -D intel=true -D libkms=true -D man-pages=true -D nouveau=false -D radeon=true -D valgrind=auto && ninja -C build"
+ /app/vmctl exec "pkg info; cd $CI_PROJECT_NAME ; meson build --auto-features=enabled -D etnaviv=disabled -D nouveau=disabled -D valgrind=disabled && ninja -C build"
set -ex
scp -r vm:$CI_PROJECT_NAME/build/meson-logs .
/app/vmctl exec "ninja -C $CI_PROJECT_NAME/build install"
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/amdgpu/amdgpu_bo.c
^
|
| @@ -533,7 +533,7 @@
amdgpu_bo_handle *buf_handle,
uint64_t *offset_in_bo)
{
- struct amdgpu_bo *bo;
+ struct amdgpu_bo *bo = NULL;
uint32_t i;
int r = 0;
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/amdgpu/amdgpu_device.c
^
|
| @@ -292,7 +292,10 @@
drm_public const char *amdgpu_get_marketing_name(amdgpu_device_handle dev)
{
- return dev->marketing_name;
+ if (dev->marketing_name)
+ return dev->marketing_name;
+ else
+ return "AMD Radeon Graphics";
}
drm_public int amdgpu_query_sw_info(amdgpu_device_handle dev,
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/core-symbols.txt
^
|
| @@ -103,11 +103,14 @@
drmModeAtomicMerge
drmModeAtomicSetCursor
drmModeAttachMode
+drmModeConnectorGetPossibleCrtcs
drmModeConnectorSetProperty
+drmModeCreateDumbBuffer
drmModeCreateLease
drmModeCreatePropertyBlob
drmModeCrtcGetGamma
drmModeCrtcSetGamma
+drmModeDestroyDumbBuffer
drmModeDestroyPropertyBlob
drmModeDetachMode
drmModeDirtyFB
@@ -126,6 +129,7 @@
drmModeFreeResources
drmModeGetConnector
drmModeGetConnectorCurrent
+drmModeGetConnectorTypeName
drmModeGetCrtc
drmModeGetEncoder
drmModeGetFB
@@ -137,6 +141,7 @@
drmModeGetPropertyBlob
drmModeGetResources
drmModeListLessees
+drmModeMapDumbBuffer
drmModeMoveCursor
drmModeObjectGetProperties
drmModeObjectSetProperty
@@ -201,3 +206,4 @@
drmWaitVBlank
drmGetFormatModifierName
drmGetFormatModifierVendor
+drmGetFormatName
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/data/amdgpu.ids
^
|
| @@ -4,120 +4,177 @@
# device_id, revision_id, product_name <-- single tab after comma
1.0.0
-15DD, C3, AMD Radeon Vega 3 Graphics
-15DD, CB, AMD Radeon Vega 3 Graphics
-15DD, CE, AMD Radeon Vega 3 Graphics
-15DD, D8, AMD Radeon Vega 3 Graphics
-15DD, CC, AMD Radeon Vega 6 Graphics
-15DD, D9, AMD Radeon Vega 6 Graphics
-15DD, C2, AMD Radeon Vega 8 Graphics
-15DD, C4, AMD Radeon Vega 8 Graphics
-15DD, C8, AMD Radeon Vega 8 Graphics
-15DD, CA, AMD Radeon Vega 8 Graphics
-15DD, D1, AMD Radeon Vega 8 Graphics
-15DD, D5, AMD Radeon Vega 8 Graphics
-15DD, D7, AMD Radeon Vega 8 Graphics
-15DD, C3, AMD Radeon Vega 10 Graphics
-15DD, D0, AMD Radeon Vega 10 Graphics
-15DD, C1, AMD Radeon Vega 11 Graphics
-15DD, C6, AMD Radeon Vega 11 Graphics
-15DD, C9, AMD Radeon Vega 11 Graphics
-15DD, D3, AMD Radeon Vega 11 Graphics
-15DD, D6, AMD Radeon Vega 11 Graphics
-15DD, 81, AMD Ryzen Embedded V1807B with Radeon Vega Gfx
-15DD, 82, AMD Ryzen Embedded V1756B with Radeon Vega Gfx
-15DD, 83, AMD Ryzen Embedded V1605B with Radeon Vega Gfx
-15DD, 85, AMD Ryzen Embedded V1202B with Radeon Vega Gfx
+1309, 00, AMD Radeon R7 Graphics
+130A, 00, AMD Radeon R6 Graphics
+130B, 00, AMD Radeon R4 Graphics
+130C, 00, AMD Radeon R7 Graphics
+130D, 00, AMD Radeon R6 Graphics
+130E, 00, AMD Radeon R5 Graphics
+130F, 00, AMD Radeon R7 Graphics
+130F, D4, AMD Radeon R7 Graphics
+130F, D5, AMD Radeon R7 Graphics
+130F, D6, AMD Radeon R7 Graphics
+130F, D7, AMD Radeon R7 Graphics
+1313, 00, AMD Radeon R7 Graphics
+1313, D4, AMD Radeon R7 Graphics
+1313, D5, AMD Radeon R7 Graphics
+1313, D6, AMD Radeon R7 Graphics
+1315, 00, AMD Radeon R5 Graphics
+1315, D4, AMD Radeon R5 Graphics
+1315, D5, AMD Radeon R5 Graphics
+1315, D6, AMD Radeon R5 Graphics
+1315, D7, AMD Radeon R5 Graphics
+1316, 00, AMD Radeon R5 Graphics
+1318, 00, AMD Radeon R5 Graphics
+131B, 00, AMD Radeon R4 Graphics
+131C, 00, AMD Radeon R7 Graphics
+131D, 00, AMD Radeon R6 Graphics
+15D8, 00, AMD Radeon RX Vega 8 Graphics WS
+15D8, 91, AMD Radeon Vega 3 Graphics
+15D8, 91, AMD Ryzen Embedded R1606G with Radeon Vega Gfx
+15D8, 92, AMD Radeon Vega 3 Graphics
+15D8, 92, AMD Ryzen Embedded R1505G with Radeon Vega Gfx
15D8, 93, AMD Radeon Vega 1 Graphics
+15D8, A1, AMD Radeon Vega 10 Graphics
+15D8, A2, AMD Radeon Vega 8 Graphics
+15D8, A3, AMD Radeon Vega 6 Graphics
+15D8, A4, AMD Radeon Vega 3 Graphics
+15D8, B1, AMD Radeon Vega 10 Graphics
+15D8, B2, AMD Radeon Vega 8 Graphics
+15D8, B3, AMD Radeon Vega 6 Graphics
+15D8, B4, AMD Radeon Vega 3 Graphics
+15D8, C1, AMD Radeon Vega 10 Graphics
+15D8, C2, AMD Radeon Vega 8 Graphics
+15D8, C3, AMD Radeon Vega 6 Graphics
15D8, C4, AMD Radeon Vega 3 Graphics
15D8, C5, AMD Radeon Vega 3 Graphics
+15D8, C8, AMD Radeon Vega 11 Graphics
+15D8, C9, AMD Radeon Vega 8 Graphics
+15D8, CA, AMD Radeon Vega 11 Graphics
+15D8, CB, AMD Radeon Vega 8 Graphics
15D8, CC, AMD Radeon Vega 3 Graphics
15D8, CE, AMD Radeon Vega 3 Graphics
-15D8, CF, AMD Radeon Vega 3 Graphics
+15D8, CF, AMD Ryzen Embedded R1305G with Radeon Vega Gfx
+15D8, D1, AMD Radeon Vega 10 Graphics
+15D8, D2, AMD Radeon Vega 8 Graphics
+15D8, D3, AMD Radeon Vega 6 Graphics
15D8, D4, AMD Radeon Vega 3 Graphics
+15D8, D8, AMD Radeon Vega 11 Graphics
+15D8, D9, AMD Radeon Vega 8 Graphics
+15D8, DA, AMD Radeon Vega 11 Graphics
+15D8, DB, AMD Radeon Vega 3 Graphics
+15D8, DB, AMD Radeon Vega 8 Graphics
15D8, DC, AMD Radeon Vega 3 Graphics
15D8, DD, AMD Radeon Vega 3 Graphics
15D8, DE, AMD Radeon Vega 3 Graphics
15D8, DF, AMD Radeon Vega 3 Graphics
15D8, E3, AMD Radeon Vega 3 Graphics
-15D8, E4, AMD Radeon Vega 3 Graphics
-15D8, A3, AMD Radeon Vega 6 Graphics
-15D8, B3, AMD Radeon Vega 6 Graphics
-15D8, C3, AMD Radeon Vega 6 Graphics
-15D8, D3, AMD Radeon Vega 6 Graphics
-15D8, A2, AMD Radeon Vega 8 Graphics
-15D8, B2, AMD Radeon Vega 8 Graphics
-15D8, C2, AMD Radeon Vega 8 Graphics
-15D8, C9, AMD Radeon Vega 8 Graphics
-15D8, CB, AMD Radeon Vega 8 Graphics
-15D8, D2, AMD Radeon Vega 8 Graphics
-15D8, D9, AMD Radeon Vega 8 Graphics
-15D8, DB, AMD Radeon Vega 8 Graphics
-15D8, A1, AMD Radeon Vega 10 Graphics
-15D8, B1, AMD Radeon Vega 10 Graphics
-15D8, C1, AMD Radeon Vega 10 Graphics
-15D8, D1, AMD Radeon Vega 10 Graphics
-15D8, C8, AMD Radeon Vega 11 Graphics
-15D8, CA, AMD Radeon Vega 11 Graphics
-15D8, D8, AMD Radeon Vega 11 Graphics
-15D8, DA, AMD Radeon Vega 11 Graphics
-15D8, 91, AMD Ryzen Embedded R1606G with Radeon Vega Gfx
-15D8, 92, AMD Ryzen Embedded R1505G with Radeon Vega Gfx
-15D8, CF, AMD Ryzen Embedded R1305G with Radeon Vega Gfx
15D8, E4, AMD Ryzen Embedded R1102G with Radeon Vega Gfx
+15DD, 81, AMD Ryzen Embedded V1807B with Radeon Vega Gfx
+15DD, 82, AMD Ryzen Embedded V1756B with Radeon Vega Gfx
+15DD, 83, AMD Ryzen Embedded V1605B with Radeon Vega Gfx
+15DD, 84, AMD Radeon Vega 6 Graphics
+15DD, 85, AMD Ryzen Embedded V1202B with Radeon Vega Gfx
+15DD, 86, AMD Radeon Vega 11 Graphics
+15DD, 88, AMD Radeon Vega 8 Graphics
+15DD, C1, AMD Radeon Vega 11 Graphics
+15DD, C2, AMD Radeon Vega 8 Graphics
+15DD, C3, AMD Radeon Vega 3 / 10 Graphics
+15DD, C4, AMD Radeon Vega 8 Graphics
+15DD, C5, AMD Radeon Vega 3 Graphics
+15DD, C6, AMD Radeon Vega 11 Graphics
+15DD, C8, AMD Radeon Vega 8 Graphics
+15DD, C9, AMD Radeon Vega 11 Graphics
+15DD, CA, AMD Radeon Vega 8 Graphics
+15DD, CB, AMD Radeon Vega 3 Graphics
+15DD, CC, AMD Radeon Vega 6 Graphics
+15DD, CE, AMD Radeon Vega 3 Graphics
+15DD, CF, AMD Radeon Vega 3 Graphics
+15DD, D0, AMD Radeon Vega 10 Graphics
+15DD, D1, AMD Radeon Vega 8 Graphics
+15DD, D3, AMD Radeon Vega 11 Graphics
+15DD, D5, AMD Radeon Vega 8 Graphics
+15DD, D6, AMD Radeon Vega 11 Graphics
+15DD, D7, AMD Radeon Vega 8 Graphics
+15DD, D8, AMD Radeon Vega 3 Graphics
+15DD, D9, AMD Radeon Vega 6 Graphics
+15DD, E1, AMD Radeon Vega 3 Graphics
+15DD, E2, AMD Radeon Vega 3 Graphics
163F, AE, AMD Custom GPU 0405
-6600, 0, AMD Radeon HD 8600 / 8700M
+6600, 00, AMD Radeon HD 8600 / 8700M
6600, 81, AMD Radeon R7 M370
-6601, 0, AMD Radeon HD 8500M / 8700M
-6604, 0, AMD Radeon R7 M265 Series
+6601, 00, AMD Radeon HD 8500M / 8700M
+6604, 00, AMD Radeon R7 M265 Series
6604, 81, AMD Radeon R7 M350
-6605, 0, AMD Radeon R7 M260 Series
+6605, 00, AMD Radeon R7 M260 Series
6605, 81, AMD Radeon R7 M340
-6606, 0, AMD Radeon HD 8790M
-6607, 0, AMD Radeon HD 8530M
-6608, 0, AMD FirePro W2100
-6610, 0, AMD Radeon HD 8600 Series
+6606, 00, AMD Radeon HD 8790M
+6607, 00, AMD Radeon R5 M240
+6608, 00, AMD FirePro W2100
+6610, 00, AMD Radeon R7 200 Series
6610, 81, AMD Radeon R7 350
6610, 83, AMD Radeon R5 340
-6611, 0, AMD Radeon HD 8500 Series
-6613, 0, AMD Radeon HD 8500 series
+6610, 87, AMD Radeon R7 200 Series
+6611, 00, AMD Radeon R7 200 Series
+6611, 87, AMD Radeon R7 200 Series
+6613, 00, AMD Radeon R7 200 Series
+6617, 00, AMD Radeon R7 240 Series
+6617, 87, AMD Radeon R7 200 Series
6617, C7, AMD Radeon R7 240 Series
-6640, 0, AMD Radeon HD 8950
+6640, 00, AMD Radeon HD 8950
6640, 80, AMD Radeon R9 M380
-6646, 0, AMD Radeon R9 M280X
+6646, 00, AMD Radeon R9 M280X
+6646, 80, AMD Radeon R9 M385
6646, 80, AMD Radeon R9 M470X
-6647, 0, AMD Radeon R9 M270X
+6647, 00, AMD Radeon R9 M200X Series
6647, 80, AMD Radeon R9 M380
-6649, 0, AMD FirePro W5100
-6658, 0, AMD Radeon R7 200 Series
-665C, 0, AMD Radeon HD 7700 Series
-665D, 0, AMD Radeon R7 200 Series
-665F, 81, AMD Radeon R7 300 Series
-6660, 0, AMD Radeon HD 8600M Series
+6649, 00, AMD FirePro W5100
+6658, 00, AMD Radeon R7 200 Series
+665C, 00, AMD Radeon HD 7700 Series
+665D, 00, AMD Radeon R7 200 Series
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/gen_table_fourcc.py
^
|
| @@ -56,7 +56,7 @@
that script instead of adding here entries manually! */
static const struct drmFormatModifierInfo drm_format_modifier_table[] = {
''')
- f.write(' { DRM_MODIFIER_INVALID(NONE, INVALID_MODIFIER) },\n')
+ f.write(' { DRM_MODIFIER_INVALID(NONE, INVALID) },\n')
f.write(' { DRM_MODIFIER_LINEAR(NONE, LINEAR) },\n')
for entry in fm_re['intel']:
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/include/drm/amdgpu_drm.h
^
|
| @@ -553,6 +553,10 @@
#define AMDGPU_HW_IP_VCE 4
#define AMDGPU_HW_IP_UVD_ENC 5
#define AMDGPU_HW_IP_VCN_DEC 6
+/*
+ * From VCN4, AMDGPU_HW_IP_VCN_ENC is re-used to support
+ * both encoding and decoding jobs.
+ */
#define AMDGPU_HW_IP_VCN_ENC 7
#define AMDGPU_HW_IP_VCN_JPEG 8
#define AMDGPU_HW_IP_NUM 9
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/include/drm/drm_fourcc.h
^
|
| @@ -99,12 +99,42 @@
#define DRM_FORMAT_INVALID 0
/* color index */
+#define DRM_FORMAT_C1 fourcc_code('C', '1', ' ', ' ') /* [7:0] C0:C1:C2:C3:C4:C5:C6:C7 1:1:1:1:1:1:1:1 eight pixels/byte */
+#define DRM_FORMAT_C2 fourcc_code('C', '2', ' ', ' ') /* [7:0] C0:C1:C2:C3 2:2:2:2 four pixels/byte */
+#define DRM_FORMAT_C4 fourcc_code('C', '4', ' ', ' ') /* [7:0] C0:C1 4:4 two pixels/byte */
#define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
-/* 8 bpp Red */
+/* 1 bpp Darkness (inverse relationship between channel value and brightness) */
+#define DRM_FORMAT_D1 fourcc_code('D', '1', ' ', ' ') /* [7:0] D0:D1:D2:D3:D4:D5:D6:D7 1:1:1:1:1:1:1:1 eight pixels/byte */
+
+/* 2 bpp Darkness (inverse relationship between channel value and brightness) */
+#define DRM_FORMAT_D2 fourcc_code('D', '2', ' ', ' ') /* [7:0] D0:D1:D2:D3 2:2:2:2 four pixels/byte */
+
+/* 4 bpp Darkness (inverse relationship between channel value and brightness) */
+#define DRM_FORMAT_D4 fourcc_code('D', '4', ' ', ' ') /* [7:0] D0:D1 4:4 two pixels/byte */
+
+/* 8 bpp Darkness (inverse relationship between channel value and brightness) */
+#define DRM_FORMAT_D8 fourcc_code('D', '8', ' ', ' ') /* [7:0] D */
+
+/* 1 bpp Red (direct relationship between channel value and brightness) */
+#define DRM_FORMAT_R1 fourcc_code('R', '1', ' ', ' ') /* [7:0] R0:R1:R2:R3:R4:R5:R6:R7 1:1:1:1:1:1:1:1 eight pixels/byte */
+
+/* 2 bpp Red (direct relationship between channel value and brightness) */
+#define DRM_FORMAT_R2 fourcc_code('R', '2', ' ', ' ') /* [7:0] R0:R1:R2:R3 2:2:2:2 four pixels/byte */
+
+/* 4 bpp Red (direct relationship between channel value and brightness) */
+#define DRM_FORMAT_R4 fourcc_code('R', '4', ' ', ' ') /* [7:0] R0:R1 4:4 two pixels/byte */
+
+/* 8 bpp Red (direct relationship between channel value and brightness) */
#define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
-/* 16 bpp Red */
+/* 10 bpp Red (direct relationship between channel value and brightness) */
+#define DRM_FORMAT_R10 fourcc_code('R', '1', '0', ' ') /* [15:0] x:R 6:10 little endian */
+
+/* 12 bpp Red (direct relationship between channel value and brightness) */
+#define DRM_FORMAT_R12 fourcc_code('R', '1', '2', ' ') /* [15:0] x:R 4:12 little endian */
+
+/* 16 bpp Red (direct relationship between channel value and brightness) */
#define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
/* 16 bpp RG */
@@ -199,7 +229,9 @@
#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
+#define DRM_FORMAT_AVUY8888 fourcc_code('A', 'V', 'U', 'Y') /* [31:0] A:Cr:Cb:Y 8:8:8:8 little endian */
#define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
+#define DRM_FORMAT_XVUY8888 fourcc_code('X', 'V', 'U', 'Y') /* [31:0] X:Cr:Cb:Y 8:8:8:8 little endian */
#define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
#define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */
@@ -308,6 +340,13 @@
*/
#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
+/* 2 plane YCbCr420.
+ * 3 10 bit components and 2 padding bits packed into 4 bytes.
+ * index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian
+ * index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0 [2:10:10:10:2:10:10:10] little endian
+ */
+#define DRM_FORMAT_P030 fourcc_code('P', '0', '3', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel packed */
+
/* 3 plane non-subsampled (444) YCbCr
* 16 bits per component, but only 10 bits are used and 6 bits are padded
* index 0: Y plane, [15:0] Y:x [10:6] little endian
@@ -373,6 +412,12 @@
#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
+#define fourcc_mod_get_vendor(modifier) \
+ (((modifier) >> 56) & 0xff)
+
+#define fourcc_mod_is_vendor(modifier, vendor) \
+ (fourcc_mod_get_vendor(modifier) == DRM_FORMAT_MOD_VENDOR_## vendor)
+
#define fourcc_mod_code(vendor, val) \
((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
@@ -540,7 +585,7 @@
*
* The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
* and at index 1. The clear color is stored at index 2, and the pitch should
- * be ignored. The clear color structure is 256 bits. The first 128 bits
+ * be 64 bytes aligned. The clear color structure is 256 bits. The first 128 bits
* represents Raw Clear Color Red, Green, Blue and Alpha color each represented
* by 32 bits. The raw clear color is consumed by the 3d engine and generates
* the converted clear color of size 64 bits. The first 32 bits store the Lower
@@ -554,6 +599,53 @@
#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
/*
+ * Intel Tile 4 layout
+ *
+ * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
+ * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It
+ * only differs from Tile Y at the 256B granularity in between. At this
+ * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
+ * of 64B x 8 rows.
+ */
+#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9)
+
+/*
+ * Intel color control surfaces (CCS) for DG2 render compression.
+ *
+ * The main surface is Tile 4 and at plane index 0. The CCS data is stored
+ * outside of the GEM object in a reserved memory area dedicated for the
+ * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
+ * main surface pitch is required to be a multiple of four Tile 4 widths.
+ */
+#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 10)
+
+/*
+ * Intel color control surfaces (CCS) for DG2 media compression.
+ *
+ * The main surface is Tile 4 and at plane index 0. For semi-planar formats
+ * like NV12, the Y and UV planes are Tile 4 and are located at plane indices
+ * 0 and 1, respectively. The CCS for all planes are stored outside of the
+ * GEM object in a reserved memory area dedicated for the storage of the
+ * CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface
+ * pitch is required to be a multiple of four Tile 4 widths.
+ */
+#define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11)
+
+/*
+ * Intel Color Control Surface with Clear Color (CCS) for DG2 render compression.
+ *
+ * The main surface is Tile 4 and at plane index 0. The CCS data is stored
+ * outside of the GEM object in a reserved memory area dedicated for the
+ * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
+ * main surface pitch is required to be a multiple of four Tile 4 widths. The
+ * clear color is stored at plane index 1 and the pitch should be 64 bytes
+ * aligned. The format of the 256 bits of clear color data matches the one used
+ * for the I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description
+ * for details.
+ */
+#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12)
+
+/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
* Macroblocks are laid in a Z-shape, and each pixel data is following the
@@ -590,6 +682,28 @@
*/
#define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
+/*
+ * Qualcomm Tiled Format
+ *
+ * Similar to DRM_FORMAT_MOD_QCOM_COMPRESSED but not compressed.
+ * Implementation may be platform and base-format specific.
+ *
+ * Each macrotile consists of m x n (mostly 4 x 4) tiles.
+ * Pixel data pitch/stride is aligned with macrotile width.
+ * Pixel data height is aligned with macrotile height.
+ * Entire pixel data buffer is aligned with 4k(bytes).
+ */
+#define DRM_FORMAT_MOD_QCOM_TILED3 fourcc_mod_code(QCOM, 3)
+
+/*
+ * Qualcomm Alternate Tiled Format
+ *
+ * Alternate tiled format typically only used within GMEM.
+ * Implementation may be platform and base-format specific.
+ */
+#define DRM_FORMAT_MOD_QCOM_TILED2 fourcc_mod_code(QCOM, 2)
+
+
/* Vivante framebuffer modifiers */
/*
@@ -630,6 +744,35 @@
*/
#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
+/*
+ * Vivante TS (tile-status) buffer modifiers. They can be combined with all of
+ * the color buffer tiling modifiers defined above. When TS is present it's a
+ * separate buffer containing the clear/compression status of each tile. The
+ * modifiers are defined as VIVANTE_MOD_TS_c_s, where c is the color buffer
+ * tile size in bytes covered by one entry in the status buffer and s is the
+ * number of status bits per entry.
+ * We reserve the top 8 bits of the Vivante modifier space for tile status
+ * clear/compression modifiers, as future cores might add some more TS layout
+ * variations.
+ */
+#define VIVANTE_MOD_TS_64_4 (1ULL << 48)
+#define VIVANTE_MOD_TS_64_2 (2ULL << 48)
+#define VIVANTE_MOD_TS_128_4 (3ULL << 48)
+#define VIVANTE_MOD_TS_256_4 (4ULL << 48)
+#define VIVANTE_MOD_TS_MASK (0xfULL << 48)
+
+/*
+ * Vivante compression modifiers. Those depend on a TS modifier being present
+ * as the TS bits get reinterpreted as compression tags instead of simple
+ * clear markers when compression is enabled.
+ */
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/include/drm/i915_drm.h
^
|
| @@ -55,15 +55,15 @@
* cause the related events to not be seen.
*
* I915_RESET_UEVENT - Event is generated just before an attempt to reset the
- * the GPU. The value supplied with the event is always 1. NOTE: Disable
+ * GPU. The value supplied with the event is always 1. NOTE: Disable
* reset via module parameter will cause this event to not be seen.
*/
#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR"
#define I915_ERROR_UEVENT "ERROR"
#define I915_RESET_UEVENT "RESET"
-/*
- * i915_user_extension: Base class for defining a chain of extensions
+/**
+ * struct i915_user_extension - Base class for defining a chain of extensions
*
* Many interfaces need to grow over time. In most cases we can simply
* extend the struct and have userspace pass in more data. Another option,
@@ -76,12 +76,58 @@
* increasing complexity, and for large parts of that interface to be
* entirely optional. The downside is more pointer chasing; chasing across
* the boundary with pointers encapsulated inside u64.
+ *
+ * Example chaining:
+ *
+ * .. code-block:: C
+ *
+ * struct i915_user_extension ext3 {
+ * .next_extension = 0, // end
+ * .name = ...,
+ * };
+ * struct i915_user_extension ext2 {
+ * .next_extension = (uintptr_t)&ext3,
+ * .name = ...,
+ * };
+ * struct i915_user_extension ext1 {
+ * .next_extension = (uintptr_t)&ext2,
+ * .name = ...,
+ * };
+ *
+ * Typically the struct i915_user_extension would be embedded in some uAPI
+ * struct, and in this case we would feed it the head of the chain(i.e ext1),
+ * which would then apply all of the above extensions.
+ *
*/
struct i915_user_extension {
+ /**
+ * @next_extension:
+ *
+ * Pointer to the next struct i915_user_extension, or zero if the end.
+ */
__u64 next_extension;
+ /**
+ * @name: Name of the extension.
+ *
+ * Note that the name here is just some integer.
+ *
+ * Also note that the name space for this is not global for the whole
+ * driver, but rather its scope/meaning is limited to the specific piece
+ * of uAPI which has embedded the struct i915_user_extension.
+ */
__u32 name;
- __u32 flags; /* All undefined bits must be zero. */
- __u32 rsvd[4]; /* Reserved for future use; must be zero. */
+ /**
+ * @flags: MBZ
+ *
+ * All undefined bits must be zero.
+ */
+ __u32 flags;
+ /**
+ * @rsvd: MBZ
+ *
+ * Reserved for future use; must be zero.
+ */
+ __u32 rsvd[4];
};
/*
@@ -108,25 +154,102 @@
I915_MOCS_CACHED,
};
-/*
+/**
+ * enum drm_i915_gem_engine_class - uapi engine type enumeration
+ *
* Different engines serve different roles, and there may be more than one
- * engine serving each role. enum drm_i915_gem_engine_class provides a
- * classification of the role of the engine, which may be used when requesting
- * operations to be performed on a certain subset of engines, or for providing
- * information about that group.
+ * engine serving each role. This enum provides a classification of the role
+ * of the engine, which may be used when requesting operations to be performed
+ * on a certain subset of engines, or for providing information about that
+ * group.
*/
enum drm_i915_gem_engine_class {
+ /**
+ * @I915_ENGINE_CLASS_RENDER:
+ *
+ * Render engines support instructions used for 3D, Compute (GPGPU),
+ * and programmable media workloads. These instructions fetch data and
+ * dispatch individual work items to threads that operate in parallel.
+ * The threads run small programs (called "kernels" or "shaders") on
+ * the GPU's execution units (EUs).
+ */
I915_ENGINE_CLASS_RENDER = 0,
+
+ /**
+ * @I915_ENGINE_CLASS_COPY:
+ *
+ * Copy engines (also referred to as "blitters") support instructions
+ * that move blocks of data from one location in memory to another,
+ * or that fill a specified location of memory with fixed data.
+ * Copy engines can perform pre-defined logical or bitwise operations
+ * on the source, destination, or pattern data.
+ */
I915_ENGINE_CLASS_COPY = 1,
+
+ /**
+ * @I915_ENGINE_CLASS_VIDEO:
+ *
+ * Video engines (also referred to as "bit stream decode" (BSD) or
+ * "vdbox") support instructions that perform fixed-function media
+ * decode and encode.
+ */
I915_ENGINE_CLASS_VIDEO = 2,
+
+ /**
+ * @I915_ENGINE_CLASS_VIDEO_ENHANCE:
+ *
+ * Video enhancement engines (also referred to as "vebox") support
+ * instructions related to image enhancement.
+ */
I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
- /* should be kept compact */
+ /**
+ * @I915_ENGINE_CLASS_COMPUTE:
+ *
+ * Compute engines support a subset of the instructions available
+ * on render engines: compute engines support Compute (GPGPU) and
+ * programmable media workloads, but do not support the 3D pipeline.
+ */
+ I915_ENGINE_CLASS_COMPUTE = 4,
+
+ /* Values in this enum should be kept compact. */
+ /**
+ * @I915_ENGINE_CLASS_INVALID:
+ *
+ * Placeholder value to represent an invalid engine class assignment.
+ */
I915_ENGINE_CLASS_INVALID = -1
};
/**
+ * struct i915_engine_class_instance - Engine class/instance identifier
+ *
+ * There may be more than one engine fulfilling any role within the system.
+ * Each engine of a class is given a unique instance number and therefore
+ * any engine can be specified by its class:instance tuplet. APIs that allow
+ * access to any engine in the system will use struct i915_engine_class_instance
+ * for this identification.
+ */
+struct i915_engine_class_instance {
+ /**
+ * @engine_class:
+ *
+ * Engine class from enum drm_i915_gem_engine_class
+ */
+ __u16 engine_class;
+#define I915_ENGINE_CLASS_INVALID_NONE -1
+#define I915_ENGINE_CLASS_INVALID_VIRTUAL -2
+
+ /**
+ * @engine_instance:
+ *
+ * Engine instance.
+ */
+ __u16 engine_instance;
+};
+
+/**
* DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
*
*/
@@ -163,8 +286,9 @@
#define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1)
#define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2)
#define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3)
+#define I915_PMU_SOFTWARE_GT_AWAKE_TIME __I915_PMU_OTHER(4)
-#define I915_PMU_LAST I915_PMU_RC6_RESIDENCY
+#define I915_PMU_LAST /* Deprecated - do not use */ I915_PMU_RC6_RESIDENCY
/* Each region is a minimum of 16k, and there are at most 255 of them.
*/
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/include/drm/tegra_drm.h
^
|
| @@ -1,27 +1,8 @@
-/*
- * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
+/* SPDX-License-Identifier: MIT */
+/* Copyright (c) 2012-2020 NVIDIA Corporation */
-#ifndef _TEGRA_DRM_H_
-#define _TEGRA_DRM_H_
+#ifndef _UAPI_TEGRA_DRM_H_
+#define _UAPI_TEGRA_DRM_H_
#include "drm.h"
@@ -29,6 +10,8 @@
extern "C" {
#endif
+/* Tegra DRM legacy UAPI. Only enabled with STAGING */
+
#define DRM_TEGRA_GEM_CREATE_TILED (1 << 0)
#define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
@@ -649,8 +632,8 @@
#define DRM_TEGRA_SYNCPT_READ 0x02
#define DRM_TEGRA_SYNCPT_INCR 0x03
#define DRM_TEGRA_SYNCPT_WAIT 0x04
-#define DRM_TEGRA_OPEN_CHANNEL 0x05
-#define DRM_TEGRA_CLOSE_CHANNEL 0x06
+#define DRM_TEGRA_OPEN_CHANNEL 0x05
+#define DRM_TEGRA_CLOSE_CHANNEL 0x06
#define DRM_TEGRA_GET_SYNCPT 0x07
#define DRM_TEGRA_SUBMIT 0x08
#define DRM_TEGRA_GET_SYNCPT_BASE 0x09
@@ -674,6 +657,402 @@
#define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags)
#define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags)
+/* New Tegra DRM UAPI */
+
+/*
+ * Reported by the driver in the `capabilities` field.
+ *
+ * DRM_TEGRA_CHANNEL_CAP_CACHE_COHERENT: If set, the engine is cache coherent
+ * with regard to the system memory.
+ */
+#define DRM_TEGRA_CHANNEL_CAP_CACHE_COHERENT (1 << 0)
+
+struct drm_tegra_channel_open {
+ /**
+ * @host1x_class: [in]
+ *
+ * Host1x class of the engine that will be programmed using this
+ * channel.
+ */
+ __u32 host1x_class;
+
+ /**
+ * @flags: [in]
+ *
+ * Flags.
+ */
+ __u32 flags;
+
+ /**
+ * @context: [out]
+ *
+ * Opaque identifier corresponding to the opened channel.
+ */
+ __u32 context;
+
+ /**
+ * @version: [out]
+ *
+ * Version of the engine hardware. This can be used by userspace
+ * to determine how the engine needs to be programmed.
+ */
+ __u32 version;
+
+ /**
+ * @capabilities: [out]
+ *
+ * Flags describing the hardware capabilities.
+ */
+ __u32 capabilities;
+ __u32 padding;
+};
+
+struct drm_tegra_channel_close {
+ /**
+ * @context: [in]
+ *
+ * Identifier of the channel to close.
+ */
+ __u32 context;
+ __u32 padding;
+};
+
+/*
+ * Mapping flags that can be used to influence how the mapping is created.
+ *
+ * DRM_TEGRA_CHANNEL_MAP_READ: create mapping that allows HW read access
+ * DRM_TEGRA_CHANNEL_MAP_WRITE: create mapping that allows HW write access
+ */
+#define DRM_TEGRA_CHANNEL_MAP_READ (1 << 0)
+#define DRM_TEGRA_CHANNEL_MAP_WRITE (1 << 1)
+#define DRM_TEGRA_CHANNEL_MAP_READ_WRITE (DRM_TEGRA_CHANNEL_MAP_READ | \
+ DRM_TEGRA_CHANNEL_MAP_WRITE)
+
+struct drm_tegra_channel_map {
+ /**
+ * @context: [in]
+ *
+ * Identifier of the channel to which make memory available for.
+ */
+ __u32 context;
+
+ /**
+ * @handle: [in]
+ *
+ * GEM handle of the memory to map.
+ */
+ __u32 handle;
+
+ /**
+ * @flags: [in]
+ *
+ * Flags.
+ */
+ __u32 flags;
+
+ /**
+ * @mapping: [out]
+ *
+ * Identifier corresponding to the mapping, to be used for
+ * relocations or unmapping later.
+ */
+ __u32 mapping;
+};
+
+struct drm_tegra_channel_unmap {
+ /**
+ * @context: [in]
+ *
+ * Channel identifier of the channel to unmap memory from.
+ */
+ __u32 context;
+
+ /**
+ * @mapping: [in]
+ *
+ * Mapping identifier of the memory mapping to unmap.
+ */
+ __u32 mapping;
+};
+
+/* Submission */
+
+/**
+ * Specify that bit 39 of the patched-in address should be set to switch
+ * swizzling between Tegra and non-Tegra sector layout on systems that store
+ * surfaces in system memory in non-Tegra sector layout.
+ */
+#define DRM_TEGRA_SUBMIT_RELOC_SECTOR_LAYOUT (1 << 0)
+
+struct drm_tegra_submit_buf {
+ /**
+ * @mapping: [in]
+ *
+ * Identifier of the mapping to use in the submission.
+ */
+ __u32 mapping;
+
+ /**
+ * @flags: [in]
+ *
+ * Flags.
+ */
+ __u32 flags;
+
+ /**
+ * Information for relocation patching.
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/intel/Makefile.sources
^
|
| @@ -1,12 +1,10 @@
LIBDRM_INTEL_FILES := \
- i915_pciids.h \
intel_bufmgr.c \
intel_bufmgr_priv.h \
intel_bufmgr_fake.c \
intel_bufmgr_gem.c \
intel_decode.c \
intel_chipset.h \
- intel_chipset.c \
mm.c \
mm.h \
uthash.h
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/intel/intel_bufmgr_gem.c
^
|
| @@ -1,7 +1,7 @@
/**************************************************************************
*
- * Copyright © 2007 Red Hat Inc.
- * Copyright © 2007-2012 Intel Corporation
+ * Copyright © 2007 Red Hat Inc.
+ * Copyright © 2007-2012 Intel Corporation
* Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
* All Rights Reserved.
*
@@ -28,7 +28,7 @@
*
**************************************************************************/
/*
- * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
+ * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
* Keith Whitwell <keithw-at-tungstengraphics-dot-com>
* Eric Anholt <eric@anholt.net>
* Dave Airlie <airlied@linux.ie>
@@ -1379,25 +1379,26 @@
static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
{
drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
+ drm_intel_bufmgr_gem *bufmgr_gem;
+ struct timespec time;
assert(atomic_read(&bo_gem->refcount) > 0);
- if (atomic_add_unless(&bo_gem->refcount, -1, 1)) {
- drm_intel_bufmgr_gem *bufmgr_gem =
- (drm_intel_bufmgr_gem *) bo->bufmgr;
- struct timespec time;
+ if (atomic_add_unless(&bo_gem->refcount, -1, 1))
+ return;
- clock_gettime(CLOCK_MONOTONIC, &time);
+ bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
- pthread_mutex_lock(&bufmgr_gem->lock);
+ clock_gettime(CLOCK_MONOTONIC, &time);
- if (atomic_dec_and_test(&bo_gem->refcount)) {
- drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
- drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec);
- }
+ pthread_mutex_lock(&bufmgr_gem->lock);
- pthread_mutex_unlock(&bufmgr_gem->lock);
+ if (atomic_dec_and_test(&bo_gem->refcount)) {
+ drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
+ drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec);
}
+
+ pthread_mutex_unlock(&bufmgr_gem->lock);
}
static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
@@ -3377,16 +3378,17 @@
{
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
- if (atomic_add_unless(&bufmgr_gem->refcount, -1, 1)) {
- pthread_mutex_lock(&bufmgr_list_mutex);
+ if (atomic_add_unless(&bufmgr_gem->refcount, -1, 1))
+ return;
- if (atomic_dec_and_test(&bufmgr_gem->refcount)) {
- DRMLISTDEL(&bufmgr_gem->managers);
- drm_intel_bufmgr_gem_destroy(bufmgr);
- }
+ pthread_mutex_lock(&bufmgr_list_mutex);
- pthread_mutex_unlock(&bufmgr_list_mutex);
+ if (atomic_dec_and_test(&bufmgr_gem->refcount)) {
+ DRMLISTDEL(&bufmgr_gem->managers);
+ drm_intel_bufmgr_gem_destroy(bufmgr);
}
+
+ pthread_mutex_unlock(&bufmgr_list_mutex);
}
drm_public void *drm_intel_gem_bo_map__gtt(drm_intel_bo *bo)
@@ -3588,13 +3590,9 @@
bufmgr_gem->gen = 6;
else if (IS_GEN7(bufmgr_gem->pci_device))
bufmgr_gem->gen = 7;
- else if (IS_GEN8(bufmgr_gem->pci_device))
+ else
+ /* Treat all further unmatched platforms the same as gen8 */
bufmgr_gem->gen = 8;
- else if (!intel_get_genx(bufmgr_gem->pci_device, &bufmgr_gem->gen)) {
- free(bufmgr_gem);
- bufmgr_gem = NULL;
- goto exit;
- }
if (IS_GEN3(bufmgr_gem->pci_device) &&
bufmgr_gem->gtt_size > 256*1024*1024) {
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/intel/intel_chipset.h
^
|
| @@ -331,20 +331,6 @@
#include <stdbool.h>
#include <libdrm_macros.h>
-drm_private bool intel_is_genx(unsigned int devid, int gen);
-drm_private bool intel_get_genx(unsigned int devid, int *gen);
-
-#define IS_GEN9(devid) intel_is_genx(devid, 9)
-#define IS_GEN10(devid) intel_is_genx(devid, 10)
-#define IS_GEN11(devid) intel_is_genx(devid, 11)
-#define IS_GEN12(devid) intel_is_genx(devid, 12)
-
-#define IS_9XX(dev) (IS_GEN3(dev) || \
- IS_GEN4(dev) || \
- IS_GEN5(dev) || \
- IS_GEN6(dev) || \
- IS_GEN7(dev) || \
- IS_GEN8(dev) || \
- intel_get_genx(dev, NULL))
+#define IS_9XX(dev) (!IS_GEN2(dev))
#endif /* _INTEL_CHIPSET_H */
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/intel/intel_decode.c
^
|
| @@ -3817,9 +3817,7 @@
struct drm_intel_decode *ctx;
int gen = 0;
- if (intel_get_genx(devid, &gen))
- ;
- else if (IS_GEN8(devid))
+ if (IS_GEN8(devid))
gen = 8;
else if (IS_GEN7(devid))
gen = 7;
@@ -3829,10 +3827,13 @@
gen = 5;
else if (IS_GEN4(devid))
gen = 4;
- else if (IS_9XX(devid))
+ else if (IS_GEN3(devid))
gen = 3;
else if (IS_GEN2(devid))
gen = 2;
+ else
+ /* Just assume future unknown platforms behave as gen8. */
+ gen = 8;
if (!gen)
return NULL;
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/intel/meson.build
^
|
| @@ -23,7 +23,7 @@
[
files(
'intel_bufmgr.c', 'intel_bufmgr_fake.c', 'intel_bufmgr_gem.c',
- 'intel_decode.c', 'mm.c', 'intel_chipset.c',
+ 'intel_decode.c', 'mm.c',
),
config_file,
],
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/intel/test_decode.c
^
|
| @@ -86,7 +86,8 @@
compare_batch(struct drm_intel_decode *ctx, const char *batch_filename)
{
FILE *out = NULL;
- void *ptr, *ref_ptr, *batch_ptr;
+ char *ptr;
+ void *ref_ptr, *batch_ptr;
#if HAVE_OPEN_MEMSTREAM
size_t size;
#endif
@@ -106,7 +107,7 @@
* inside of an automake project's test infrastructure.
*/
#if HAVE_OPEN_MEMSTREAM
- out = open_memstream((char **)&ptr, &size);
+ out = open_memstream(&ptr, &size);
#else
fprintf(stderr, "platform lacks open_memstream, skipping.\n");
exit(77);
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/man/drm-kms.7.rst
^
|
| @@ -102,13 +102,13 @@
information.
All valid modes for a connector can be retrieved with a call to
-drmModeGetConnector3 You need to select the mode you want to use and save it.
+**drmModeGetConnector**\ (3) You need to select the mode you want to use and save it.
The first mode in the list is the default mode with the highest resolution
possible and often a suitable choice.
After you have a working connector+CRTC+mode combination, you need to create a
framebuffer that is used for scanout. Memory buffer allocation is
-driver-depedent and described in **drm-memory**\ (7). You need to create a
+driver-dependent and described in **drm-memory**\ (7). You need to create a
buffer big enough for your selected mode. Now you can create a framebuffer
object that uses your memory-buffer as scanout buffer. You can do this with
**drmModeAddFB**\ (3) and **drmModeAddFB2**\ (3).
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/man/drm.7.rst
^
|
| @@ -73,7 +73,7 @@
used by most DRM drivers. These are the *Translation Table Manager*
(TTM) and the *Graphics Execution Manager* (GEM). They provide generic
APIs to create, destroy and access buffers from user-space. However,
-there are still many differences between the drivers so driver-depedent
+there are still many differences between the drivers so driver-dependent
code is still needed. Many helpers are provided in *libgbm* (Graphics
Buffer Manager) from the *Mesa* project. For more information on DRM
memory management, see **drm-memory**\ (7).
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/meson.build
^
|
| @@ -21,12 +21,16 @@
project(
'libdrm',
['c'],
- version : '2.4.110',
+ version : '2.4.115',
license : 'MIT',
meson_version : '>= 0.53',
- default_options : ['buildtype=debugoptimized', 'c_std=c99'],
+ default_options : ['buildtype=debugoptimized', 'c_std=c11'],
)
+if ['windows', 'darwin'].contains(host_machine.system())
+ error('unsupported OS: @0@'.format(host_machine.system()))
+endif
+
pkg = import('pkgconfig')
config = configuration_data()
@@ -34,6 +38,7 @@
config.set10('UDEV', get_option('udev'))
with_freedreno_kgsl = get_option('freedreno-kgsl')
with_install_tests = get_option('install-test-programs')
+with_tests = get_option('tests')
if ['freebsd', 'dragonfly', 'netbsd'].contains(host_machine.system())
dep_pthread_stubs = dependency('pthread-stubs', version : '>= 0.4')
@@ -82,57 +87,59 @@
config.set10('HAVE_LIBDRM_ATOMIC_PRIMITIVES', intel_atomics)
config.set10('HAVE_LIB_ATOMIC_OPS', lib_atomics)
+dep_pciaccess = dependency('pciaccess', version : '>= 0.10', required : get_option('intel'))
+
with_intel = false
_intel = get_option('intel')
-if _intel != 'false'
- if _intel == 'true' and not with_atomics
+if not _intel.disabled()
+ if _intel.enabled() and not with_atomics
error('libdrm_intel requires atomics.')
else
- with_intel = _intel == 'true' or host_machine.cpu_family().startswith('x86')
+ with_intel = (_intel.enabled() or host_machine.cpu_family().startswith('x86')) and with_atomics and dep_pciaccess.found()
endif
endif
summary('Intel', with_intel)
with_radeon = false
_radeon = get_option('radeon')
-if _radeon != 'false'
- if _radeon == 'true' and not with_atomics
+if not _radeon.disabled()
+ if _radeon.enabled() and not with_atomics
error('libdrm_radeon requires atomics.')
endif
- with_radeon = true
+ with_radeon = with_atomics
endif
summary('Radeon', with_radeon)
with_amdgpu = false
_amdgpu = get_option('amdgpu')
-if _amdgpu != 'false'
- if _amdgpu == 'true' and not with_atomics
+if not _amdgpu.disabled()
+ if _amdgpu.enabled() and not with_atomics
error('libdrm_amdgpu requires atomics.')
endif
- with_amdgpu = true
+ with_amdgpu = with_atomics
endif
summary('AMDGPU', with_amdgpu)
with_nouveau = false
_nouveau = get_option('nouveau')
-if _nouveau != 'false'
- if _nouveau == 'true' and not with_atomics
+if not _nouveau.disabled()
+ if _nouveau.enabled() and not with_atomics
error('libdrm_nouveau requires atomics.')
endif
- with_nouveau = true
+ with_nouveau = with_atomics
endif
summary('Nouveau', with_nouveau)
with_vmwgfx = false
_vmwgfx = get_option('vmwgfx')
-if _vmwgfx != 'false'
+if not _vmwgfx.disabled()
with_vmwgfx = true
endif
summary('vmwgfx', with_vmwgfx)
with_omap = false
_omap = get_option('omap')
-if _omap == 'true'
+if _omap.enabled()
if not with_atomics
error('libdrm_omap requires atomics.')
endif
@@ -142,11 +149,11 @@
with_freedreno = false
_freedreno = get_option('freedreno')
-if _freedreno != 'false'
- if _freedreno == 'true' and not with_atomics
+if not _freedreno.disabled()
+ if _freedreno.enabled() and not with_atomics
error('libdrm_freedreno requires atomics.')
else
- with_freedreno = _freedreno == 'true' or ['arm', 'aarch64'].contains(host_machine.cpu_family())
+ with_freedreno = (_freedreno.enabled() or ['arm', 'aarch64'].contains(host_machine.cpu_family())) and with_atomics
endif
endif
summary('Freedreno', with_freedreno)
@@ -154,7 +161,7 @@
with_tegra = false
_tegra = get_option('tegra')
-if _tegra == 'true'
+if _tegra.enabled()
if not with_atomics
error('libdrm_tegra requires atomics.')
endif
@@ -164,33 +171,29 @@
with_etnaviv = false
_etnaviv = get_option('etnaviv')
-if _etnaviv == 'true'
- if not with_atomics
+if not _etnaviv.disabled()
+ if _etnaviv.enabled() and not with_atomics
error('libdrm_etnaviv requires atomics.')
endif
- with_etnaviv = true
+ with_etnaviv = _etnaviv.enabled() or (
+ with_atomics and [
+ 'loongarch64', 'mips', 'mips64',
+ 'arm', 'aarch64', 'arc',
+ ].contains(host_machine.cpu_family())
+ )
endif
summary('Etnaviv', with_etnaviv)
-with_exynos = get_option('exynos') == 'true'
+with_exynos = get_option('exynos').enabled()
summary('EXYNOS', with_exynos)
with_vc4 = false
_vc4 = get_option('vc4')
-if _vc4 != 'false'
- with_vc4 = _vc4 == 'true' or ['arm', 'aarch64'].contains(host_machine.cpu_family())
+if not _vc4.disabled()
+ with_vc4 = _vc4.enabled() or ['arm', 'aarch64'].contains(host_machine.cpu_family())
endif
summary('VC4', with_vc4)
-# XXX: Apparently only freebsd and dragonfly bsd actually need this (and
-# gnu/kfreebsd), not openbsd and netbsd
-with_libkms = false
-_libkms = get_option('libkms')
-if _libkms != 'false'
- with_libkms = _libkms == 'true' or (['linux', 'freebsd', 'dragonfly'].contains(host_machine.system()) and not android)
-endif
-summary('libkms', with_libkms)
-
# Among others FreeBSD does not have a separate dl library.
if not cc.has_function('dlsym')
dep_dl = cc.find_library('dl', required : with_nouveau)
@@ -243,32 +246,19 @@
'-Wno-unused-parameter', '-Wno-attributes', '-Wno-long-long',
'-Wno-missing-field-initializers'])
-dep_pciaccess = dependency('pciaccess', version : '>= 0.10', required : with_intel)
dep_cunit = dependency('cunit', version : '>= 2.1', required : false)
-_cairo_tests = get_option('cairo-tests')
-if _cairo_tests != 'false'
- dep_cairo = dependency('cairo', required : _cairo_tests == 'true')
- with_cairo_tests = dep_cairo.found()
-else
- dep_cairo = []
- with_cairo_tests = false
-endif
-_valgrind = get_option('valgrind')
-if _valgrind != 'false'
- if with_freedreno
- dep_valgrind = dependency('valgrind', required : _valgrind == 'true', version : '>=3.10.0')
- else
- dep_valgrind = dependency('valgrind', required : _valgrind == 'true')
- endif
- with_valgrind = dep_valgrind.found()
-else
- dep_valgrind = []
- with_valgrind = false
+dep_cairo = dependency('cairo', required : get_option('cairo-tests'))
+with_cairo_tests = dep_cairo.found()
+
+valgrind_version = []
+if with_freedreno
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/meson_options.txt
^
|
| @@ -19,108 +19,76 @@
# SOFTWARE.
option(
- 'libkms',
- type : 'combo',
- value : 'auto',
- choices : ['true', 'false', 'auto'],
- description : 'Build libkms mm abstraction library.',
-)
-option(
'intel',
- type : 'combo',
- value : 'auto',
- choices : ['true', 'false', 'auto'],
+ type : 'feature',
description : '''Enable support for Intel's KMS API.''',
)
option(
'radeon',
- type : 'combo',
- value : 'auto',
- choices : ['true', 'false', 'auto'],
+ type : 'feature',
description : '''Enable support for radeons's KMS API.''',
)
option(
'amdgpu',
- type : 'combo',
- value : 'auto',
- choices : ['true', 'false', 'auto'],
+ type : 'feature',
description : '''Enable support for amdgpu's KMS API.''',
)
option(
'nouveau',
- type : 'combo',
- value : 'auto',
- choices : ['true', 'false', 'auto'],
+ type : 'feature',
description : '''Enable support for nouveau's KMS API.''',
)
option(
'vmwgfx',
- type : 'combo',
- value : 'true',
- choices : ['true', 'false', 'auto'],
+ type : 'feature',
description : '''Enable support for vmgfx's KMS API.''',
)
option(
'omap',
- type : 'combo',
- value : 'false',
- choices : ['true', 'false', 'auto'],
+ type : 'feature',
+ value : 'disabled',
description : '''Enable support for OMAP's experimental KMS API.''',
)
option(
'exynos',
- type : 'combo',
- value : 'false',
- choices : ['true', 'false', 'auto'],
+ type : 'feature',
+ value : 'disabled',
description : '''Enable support for EXYNOS's experimental KMS API.''',
)
option(
'freedreno',
- type : 'combo',
- value : 'auto',
- choices : ['true', 'false', 'auto'],
+ type : 'feature',
description : '''Enable support for freedreno's KMS API.''',
)
option(
'tegra',
- type : 'combo',
- value : 'false',
- choices : ['true', 'false', 'auto'],
+ type : 'feature',
+ value : 'disabled',
description : '''Enable support for Tegra's experimental KMS API.''',
)
option(
'vc4',
- type : 'combo',
- value : 'auto',
- choices : ['true', 'false', 'auto'],
+ type : 'feature',
description : '''Enable support for vc4's KMS API.''',
)
option(
'etnaviv',
- type : 'combo',
- value : 'false',
- choices : ['true', 'false', 'auto'],
- description : '''Enable support for etnaviv's experimental KMS API.''',
+ type : 'feature',
+ description : '''Enable support for etnaviv's KMS API.''',
)
option(
'cairo-tests',
- type : 'combo',
- value : 'auto',
- choices : ['true', 'false', 'auto'],
+ type : 'feature',
description : 'Enable support for Cairo rendering in tests.',
)
option(
'man-pages',
- type : 'combo',
- value : 'auto',
- choices : ['true', 'false', 'auto'],
+ type : 'feature',
description : 'Enable manpage generation and installation.',
)
option(
'valgrind',
- type : 'combo',
- value : 'auto',
- choices : ['true', 'false', 'auto'],
+ type : 'feature',
description : 'Build libdrm with valgrind support.',
)
option(
@@ -141,3 +109,9 @@
value : false,
description : 'Enable support for using udev instead of mknod.',
)
+option(
+ 'tests',
+ type : 'boolean',
+ value : true,
+ description : 'Build test programs.',
+)
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/nouveau/nouveau-symbols.txt
^
|
| @@ -12,6 +12,7 @@
nouveau_bufctx_new
nouveau_bufctx_refn
nouveau_bufctx_reset
+nouveau_check_dead_channel
nouveau_client_del
nouveau_client_new
nouveau_device_del
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/nouveau/nouveau.h
^
|
| @@ -273,4 +273,8 @@
uint32_t offset;
uint32_t length;
};
+
+bool
+nouveau_check_dead_channel(struct nouveau_drm *, struct nouveau_object *chan);
+
#endif
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/nouveau/pushbuf.c
^
|
| @@ -782,3 +782,19 @@
pushbuf_flush(push);
return pushbuf_validate(push, false);
}
+
+drm_public bool
+nouveau_check_dead_channel(struct nouveau_drm *drm, struct nouveau_object *chan)
+{
+ struct drm_nouveau_gem_pushbuf req = {};
+ struct nouveau_fifo *fifo = chan->data;
+ int ret;
+
+ req.channel = fifo->channel;
+ req.nr_push = 0;
+
+ ret = drmCommandWriteRead(drm->fd, DRM_NOUVEAU_GEM_PUSHBUF,
+ &req, sizeof(req));
+ /* nouveau returns ENODEV once the channel was killed */
+ return ret == -ENODEV;
+}
|
|
[-]
[+]
|
Added |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tegra/channel.c
^
|
| @@ -0,0 +1,195 @@
+/*
+ * Copyright © 2012, 2013 Thierry Reding
+ * Copyright © 2013 Erik Faye-Lund
+ * Copyright © 2014-2021 NVIDIA Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifdef HAVE_CONFIG_H
+# include "config.h"
+#endif
+
+#include <errno.h>
+#include <string.h>
+
+#include <sys/ioctl.h>
+
+#include "private.h"
+
+drm_public int
+drm_tegra_channel_open(struct drm_tegra *drm,
+ enum drm_tegra_class client,
+ struct drm_tegra_channel **channelp)
+{
+ struct drm_tegra_channel_open args;
+ struct drm_tegra_channel *channel;
+ enum host1x_class class;
+ int err;
+
+ switch (client) {
+ case DRM_TEGRA_HOST1X:
+ class = HOST1X_CLASS_HOST1X;
+ break;
+
+ case DRM_TEGRA_GR2D:
+ class = HOST1X_CLASS_GR2D;
+ break;
+
+ case DRM_TEGRA_GR3D:
+ class = HOST1X_CLASS_GR3D;
+ break;
+
+ case DRM_TEGRA_VIC:
+ class = HOST1X_CLASS_VIC;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ channel = calloc(1, sizeof(*channel));
+ if (!channel)
+ return -ENOMEM;
+
+ channel->drm = drm;
+
+ memset(&args, 0, sizeof(args));
+ args.host1x_class = class;
+
+ err = ioctl(drm->fd, DRM_IOCTL_TEGRA_CHANNEL_OPEN, &args);
+ if (err < 0) {
+ free(channel);
+ return -errno;
+ }
+
+ channel->context = args.context;
+ channel->version = args.version;
+ channel->capabilities = args.capabilities;
+ channel->class = class;
+
+ switch (channel->version) {
+ case 0x20:
+ case 0x30:
+ case 0x35:
+ case 0x40:
+ case 0x21:
+ channel->cond_shift = 8;
+ break;
+
+ case 0x18:
+ case 0x19:
+ channel->cond_shift = 10;
+ break;
+
+ default:
+ return -ENOTSUP;
+ }
+
+ *channelp = channel;
+
+ return 0;
+}
+
+drm_public int drm_tegra_channel_close(struct drm_tegra_channel *channel)
+{
+ struct drm_tegra_channel_close args;
+ struct drm_tegra *drm;
+ int err;
+
+ if (!channel)
+ return -EINVAL;
+
+ drm = channel->drm;
+
+ memset(&args, 0, sizeof(args));
+ args.context = channel->context;
+
+ err = ioctl(drm->fd, DRM_IOCTL_TEGRA_CHANNEL_CLOSE, &args);
+ if (err < 0)
+ return -errno;
+
+ free(channel);
+
+ return 0;
+}
+
+drm_public unsigned int
+drm_tegra_channel_get_version(struct drm_tegra_channel *channel)
+{
+ return channel->version;
+}
+
+drm_public int
+drm_tegra_channel_map(struct drm_tegra_channel *channel,
+ struct drm_tegra_bo *bo, uint32_t flags,
+ struct drm_tegra_mapping **mapp)
+{
+ struct drm_tegra *drm = channel->drm;
+ struct drm_tegra_channel_map args;
+ struct drm_tegra_mapping *map;
+ int err;
+
+ if (!drm || !bo || !mapp)
+ return -EINVAL;
+
+ map = calloc(1, sizeof(*map));
+ if (!map)
+ return -ENOMEM;
+
+ memset(&args, 0, sizeof(args));
+ args.context = channel->context;
+ args.handle = bo->handle;
+ args.flags = flags;
+
+ err = ioctl(drm->fd, DRM_IOCTL_TEGRA_CHANNEL_MAP, &args);
+ if (err < 0) {
+ free(map);
+ return -errno;
+ }
+
+ map->channel = channel;
+ map->id = args.mapping;
+ *mapp = map;
+
+ return 0;
+}
+
+drm_public int
+drm_tegra_channel_unmap(struct drm_tegra_mapping *map)
+{
+ struct drm_tegra_channel *channel = map->channel;
+ struct drm_tegra *drm = channel->drm;
+ struct drm_tegra_channel_unmap args;
+ int err;
+
+ if (!channel || !map)
+ return -EINVAL;
+
+ memset(&args, 0, sizeof(args));
+ args.context = channel->context;
+ args.mapping = map->id;
+
+ err = ioctl(drm->fd, DRM_IOCTL_TEGRA_CHANNEL_UNMAP, &args);
+ if (err < 0)
+ return -errno;
+
+ free(map);
+ return 0;
+}
|
|
[-]
[+]
|
Added |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tegra/job.c
^
|
| @@ -0,0 +1,187 @@
+/*
+ * Copyright © 2012, 2013 Thierry Reding
+ * Copyright © 2013 Erik Faye-Lund
+ * Copyright © 2014 NVIDIA Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifdef HAVE_CONFIG_H
+# include "config.h"
+#endif
+
+#include <errno.h>
+#include <stdlib.h>
+#include <string.h>
+#include <time.h>
+#include <unistd.h>
+
+#include <sys/ioctl.h>
+#include <sys/poll.h>
+
+#include "private.h"
+
+struct drm_tegra_submit_cmd *
+drm_tegra_job_add_command(struct drm_tegra_job *job, uint32_t type,
+ uint32_t flags)
+{
+ struct drm_tegra_submit_cmd *commands, *command;
+ size_t size;
+
+ size = (job->num_commands + 1) * sizeof(*commands);
+
+ commands = realloc(job->commands, size);
+ if (!commands)
+ return NULL;
+
+ command = &commands[job->num_commands];
+ memset(command, 0, sizeof(*command));
+ command->type = type;
+ command->flags = flags;
+
+ job->commands = commands;
+ job->num_commands++;
+
+ return command;
+}
+
+drm_public int
+drm_tegra_job_new(struct drm_tegra_channel *channel,
+ struct drm_tegra_job **jobp)
+{
+ struct drm_tegra_job *job;
+
+ job = calloc(1, sizeof(*job));
+ if (!job)
+ return -ENOMEM;
+
+ job->page_size = sysconf(_SC_PAGESIZE);
+ job->channel = channel;
+
+ *jobp = job;
+
+ return 0;
+}
+
+drm_public int drm_tegra_job_free(struct drm_tegra_job *job)
+{
+ if (!job)
+ return -EINVAL;
+
+ if (job->pushbuf)
+ drm_tegra_pushbuf_free(job->pushbuf);
+
+ if (job->commands)
+ free(job->commands);
+
+ if (job->buffers)
+ free(job->buffers);
+
+ free(job);
+
+ return 0;
+}
+
+drm_public int
+drm_tegra_job_get_pushbuf(struct drm_tegra_job *job,
+ struct drm_tegra_pushbuf **pushbufp)
+{
+ struct drm_tegra_pushbuf *pushbuf;
+
+ if (!job->pushbuf) {
+ pushbuf = calloc(1, sizeof(*pushbuf));
+ if (!pushbuf)
+ return -ENOMEM;
+
+ pushbuf->job = job;
+
+ pushbuf->start = calloc(1, job->page_size);
+ if (!pushbuf->start) {
+ free(pushbuf);
+ return -ENOMEM;
+ }
+
+ pushbuf->end = pushbuf->start + job->page_size / 4;
+ pushbuf->ptr = pushbuf->start;
+
+ job->pushbuf = pushbuf;
+ }
+
+ *pushbufp = job->pushbuf;
+
+ return 0;
+}
+
+drm_public int
+drm_tegra_job_submit(struct drm_tegra_job *job, struct drm_tegra_fence *fence)
+{
+ struct drm_tegra_channel *channel = job->channel;
+ struct drm_tegra *drm = channel->drm;
+ struct drm_tegra_channel_submit args;
+ int err;
+
+ memset(&args, 0, sizeof(args));
+ args.context = channel->context;
+ args.num_bufs = job->num_buffers;
+ args.num_cmds = job->num_commands;
+ args.gather_data_words = job->pushbuf->ptr - job->pushbuf->start;
+ args.syncpt.id = job->syncpt.id;
+ args.syncpt.increments = job->syncpt.increments;
+
+ args.bufs_ptr = (uintptr_t)job->buffers;
+ args.cmds_ptr = (uintptr_t)job->commands;
+ args.gather_data_ptr = (uintptr_t)job->pushbuf->start;
+
+ err = ioctl(drm->fd, DRM_IOCTL_TEGRA_CHANNEL_SUBMIT, &args);
+ if (err < 0)
+ return -errno;
+
+ job->syncpt.fence = args.syncpt.value;
+
+ if (fence) {
+ fence->drm = drm;
+ fence->syncpt = job->syncpt.id;
+ fence->value = job->syncpt.fence;
+ }
+
+ return 0;
+}
+
+drm_public int
+drm_tegra_job_wait(struct drm_tegra_job *job, unsigned long timeout)
+{
+ struct drm_tegra_channel *channel = job->channel;
+ struct drm_tegra *drm = channel->drm;
+ struct drm_tegra_syncpoint_wait args;
+ struct timespec ts;
+ int err;
+
+ clock_gettime(CLOCK_MONOTONIC, &ts);
+
+ memset(&args, 0, sizeof(args));
+ args.timeout_ns = ts.tv_sec * 1000000000 + ts.tv_nsec + timeout;
+ args.id = job->syncpt.id;
+ args.threshold = job->syncpt.fence;
+
+ err = ioctl(drm->fd, DRM_IOCTL_TEGRA_SYNCPOINT_WAIT, &args);
+ if (err < 0)
+ return -errno;
+
+ return 0;
+}
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tegra/meson.build
^
|
| @@ -20,7 +20,12 @@
libdrm_tegra = library(
'drm_tegra',
- [files('tegra.c'), config_file],
+ [
+ files(
+ 'channel.c', 'job.c', 'private.h', 'pushbuf.c', 'syncpt.c', 'tegra.c'
+ ),
+ config_file
+ ],
include_directories : [inc_root, inc_drm],
link_with : libdrm,
dependencies : [dep_pthread_stubs, dep_atomic_ops],
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tegra/private.h
^
|
| @@ -26,26 +26,93 @@
#define __DRM_TEGRA_PRIVATE_H__ 1
#include <stdbool.h>
+#include <stddef.h>
#include <stdint.h>
#include <libdrm_macros.h>
#include <xf86atomic.h>
+#include "tegra_drm.h"
#include "tegra.h"
+#define container_of(ptr, type, member) ({ \
+ const __typeof__(((type *)0)->member) *__mptr = (ptr); \
+ (type *)((char *)__mptr - offsetof(type, member)); \
+ })
+
+enum host1x_class {
+ HOST1X_CLASS_HOST1X = 0x01,
+ HOST1X_CLASS_GR2D = 0x51,
+ HOST1X_CLASS_GR2D_SB = 0x52,
+ HOST1X_CLASS_VIC = 0x5d,
+ HOST1X_CLASS_GR3D = 0x60,
+};
+
struct drm_tegra {
- bool close;
- int fd;
+ bool close;
+ int fd;
};
struct drm_tegra_bo {
- struct drm_tegra *drm;
- uint32_t handle;
- uint32_t offset;
- uint32_t flags;
- uint32_t size;
- atomic_t ref;
- void *map;
+ struct drm_tegra *drm;
+ uint32_t handle;
+ uint64_t offset;
+ uint32_t flags;
+ uint32_t size;
+ atomic_t ref;
+ void *map;
+};
+
+struct drm_tegra_channel {
+ struct drm_tegra *drm;
+ enum host1x_class class;
+ uint32_t capabilities;
+ unsigned int version;
+ uint64_t context;
+
+ unsigned int cond_shift;
+};
+
+struct drm_tegra_mapping {
+ struct drm_tegra_channel *channel;
+ uint32_t id;
+};
+
+struct drm_tegra_pushbuf {
+ struct drm_tegra_job *job;
+
+ uint32_t *start;
+ uint32_t *end;
+ uint32_t *ptr;
+};
+
+void drm_tegra_pushbuf_free(struct drm_tegra_pushbuf *pushbuf);
+
+struct drm_tegra_job {
+ struct drm_tegra_channel *channel;
+ struct drm_tegra_pushbuf *pushbuf;
+ size_t page_size;
+
+ struct drm_tegra_submit_cmd *commands;
+ unsigned int num_commands;
+
+ struct drm_tegra_submit_buf *buffers;
+ unsigned int num_buffers;
+
+ struct {
+ uint32_t id;
+ uint32_t increments;
+ uint32_t fence;
+ } syncpt;
+};
+
+struct drm_tegra_submit_cmd *
+drm_tegra_job_add_command(struct drm_tegra_job *job, uint32_t type,
+ uint32_t flags);
+
+struct drm_tegra_syncpoint {
+ struct drm_tegra *drm;
+ uint32_t id;
};
#endif /* __DRM_TEGRA_PRIVATE_H__ */
|
|
[-]
[+]
|
Added |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tegra/pushbuf.c
^
|
| @@ -0,0 +1,184 @@
+/*
+ * Copyright © 2012, 2013 Thierry Reding
+ * Copyright © 2013 Erik Faye-Lund
+ * Copyright © 2014 NVIDIA Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifdef HAVE_CONFIG_H
+# include "config.h"
+#endif
+
+#include <errno.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "util_math.h"
+#include "private.h"
+
+#define HOST1X_OPCODE_NONINCR(offset, count) \
+ ((0x2 << 28) | (((offset) & 0xfff) << 16) | ((count) & 0xffff))
+
+static inline unsigned int
+drm_tegra_pushbuf_get_offset(struct drm_tegra_pushbuf *pushbuf, uint32_t *ptr)
+{
+ return ptr - pushbuf->start;
+}
+
+void drm_tegra_pushbuf_free(struct drm_tegra_pushbuf *pushbuf)
+{
+ if (pushbuf->start)
+ free(pushbuf->start);
+
+ free(pushbuf);
+}
+
+/**
+ * drm_tegra_pushbuf_begin() - prepare push buffer for a series of pushes
+ * @pushbuf: push buffer
+ * @words: maximum number of words in series of pushes to follow
+ */
+drm_public int
+drm_tegra_pushbuf_begin(struct drm_tegra_pushbuf *pushbuf,
+ unsigned int words, uint32_t **ptrp)
+{
+ struct drm_tegra_job *job = pushbuf->job;
+ unsigned long offset;
+ size_t size;
+ void *ptr;
+
+ if (pushbuf->ptr + words >= pushbuf->end) {
+ words = pushbuf->end - pushbuf->start + words;
+ size = ALIGN(words * 4, job->page_size);
+ offset = pushbuf->ptr - pushbuf->start;
+
+ ptr = realloc(pushbuf->start, size);
+ if (!ptr)
+ return -ENOMEM;
+
+ pushbuf->start = ptr;
+ pushbuf->end = pushbuf->start + size / 4;
+ pushbuf->ptr = pushbuf->start + offset;
+ }
+
+ if (ptrp)
+ *ptrp = pushbuf->ptr;
+
+ return 0;
+}
+
+drm_public int
+drm_tegra_pushbuf_end(struct drm_tegra_pushbuf *pushbuf, uint32_t *ptr)
+{
+ struct drm_tegra_submit_cmd *command;
+
+ command = drm_tegra_job_add_command(pushbuf->job,
+ DRM_TEGRA_SUBMIT_CMD_GATHER_UPTR,
+ 0);
+ if (!command)
+ return -ENOMEM;
+
+ command->gather_uptr.words = ptr - pushbuf->start;
+ pushbuf->ptr = ptr;
+
+ return 0;
+}
+
+drm_public int
+drm_tegra_pushbuf_wait(struct drm_tegra_pushbuf *pushbuf,
+ struct drm_tegra_syncpoint *syncpt,
+ uint32_t value)
+{
+ struct drm_tegra_submit_cmd *command;
+
+ command = drm_tegra_job_add_command(pushbuf->job,
+ DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT,
+ 0);
+ if (!command)
+ return -ENOMEM;
+
+ command->wait_syncpt.id = syncpt->id;
+ command->wait_syncpt.value = value;
+
+ return 0;
+}
+
+drm_public int
+drm_tegra_pushbuf_relocate(struct drm_tegra_pushbuf *pushbuf, uint32_t **ptrp,
+ struct drm_tegra_mapping *target,
+ unsigned long offset, unsigned int shift,
+ uint32_t flags)
+{
+ struct drm_tegra_submit_buf *buffers, *buffer;
+ struct drm_tegra_job *job = pushbuf->job;
+ size_t size;
+
+ size = (job->num_buffers + 1) * sizeof(*buffer);
+
+ buffers = realloc(job->buffers, size);
+ if (!buffers)
+ return -ENOMEM;
+
+ buffer = &buffers[job->num_buffers];
+
+ memset(buffer, 0, sizeof(*buffer));
+ buffer->mapping = target->id;
+ buffer->flags = flags;
+ buffer->reloc.target_offset = offset;
+ buffer->reloc.gather_offset_words = drm_tegra_pushbuf_get_offset(pushbuf,
+ *ptrp);
+ buffer->reloc.shift = shift;
+
+ *(*ptrp)++ = 0xdeadbeef;
+
+ job->buffers = buffers;
+ job->num_buffers++;
+
+ return 0;
+}
+
+drm_public int
+drm_tegra_pushbuf_sync(struct drm_tegra_pushbuf *pushbuf,
+ struct drm_tegra_syncpoint *syncpt,
+ unsigned int count)
+{
+ struct drm_tegra_job *job = pushbuf->job;
+
+ job->syncpt.increments += count;
+ job->syncpt.id = syncpt->id;
+
+ return 0;
+}
+
+drm_public int
+drm_tegra_pushbuf_sync_cond(struct drm_tegra_pushbuf *pushbuf, uint32_t **ptrp,
+ struct drm_tegra_syncpoint *syncpt,
+ enum drm_tegra_sync_cond cond)
+{
+ struct drm_tegra_channel *channel = pushbuf->job->channel;
+
+ if (cond >= DRM_TEGRA_SYNC_COND_MAX)
+ return -EINVAL;
+
+ *(*ptrp)++ = HOST1X_OPCODE_NONINCR(0x0, 0x1);
+ *(*ptrp)++ = cond << channel->cond_shift | syncpt->id;
+
+ return drm_tegra_pushbuf_sync(pushbuf, syncpt, 1);
+}
|
|
[-]
[+]
|
Added |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tegra/syncpt.c
^
|
| @@ -0,0 +1,101 @@
+/*
+ * Copyright © 2021 NVIDIA Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifdef HAVE_CONFIG_H
+# include "config.h"
+#endif
+
+#include <errno.h>
+#include <string.h>
+
+#include <sys/ioctl.h>
+
+#include "private.h"
+
+drm_public int
+drm_tegra_syncpoint_new(struct drm_tegra *drm,
+ struct drm_tegra_syncpoint **syncptp)
+{
+ struct drm_tegra_syncpoint_allocate args;
+ struct drm_tegra_syncpoint *syncpt;
+ int err;
+
+ syncpt = calloc(1, sizeof(*syncpt));
+ if (!syncpt)
+ return -ENOMEM;
+
+ memset(&args, 0, sizeof(args));
+
+ err = ioctl(drm->fd, DRM_IOCTL_TEGRA_SYNCPOINT_ALLOCATE, &args);
+ if (err < 0) {
+ free(syncpt);
+ return -errno;
+ }
+
+ syncpt->drm = drm;
+ syncpt->id = args.id;
+
+ *syncptp = syncpt;
+
+ return 0;
+}
+
+drm_public int
+drm_tegra_syncpoint_free(struct drm_tegra_syncpoint *syncpt)
+{
+ struct drm_tegra_syncpoint_free args;
+ struct drm_tegra *drm = syncpt->drm;
+ int err;
+
+ if (!syncpt)
+ return -EINVAL;
+
+ memset(&args, 0, sizeof(args));
+ args.id = syncpt->id;
+
+ err = ioctl(drm->fd, DRM_IOCTL_TEGRA_SYNCPOINT_FREE, &args);
+ if (err < 0)
+ return -errno;
+
+ free(syncpt);
+
+ return 0;
+}
+
+drm_public int
+drm_tegra_fence_wait(struct drm_tegra_fence *fence, unsigned long timeout)
+{
+ struct drm_tegra_syncpoint_wait args;
+ struct drm_tegra *drm = fence->drm;
+ int err;
+
+ memset(&args, 0, sizeof(args));
+ args.timeout_ns = 0;
+ args.id = fence->syncpt;
+ args.threshold = fence->value;
+
+ err = ioctl(drm->fd, DRM_IOCTL_TEGRA_SYNCPOINT_WAIT, &args);
+ if (err < 0)
+ return -errno;
+
+ return 0;
+}
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tegra/tegra-symbols.txt
^
|
| @@ -1,13 +1,32 @@
-drm_tegra_bo_get_flags
+drm_tegra_bo_export
drm_tegra_bo_get_handle
-drm_tegra_bo_get_tiling
+drm_tegra_bo_get_name
+drm_tegra_bo_import
drm_tegra_bo_map
drm_tegra_bo_new
+drm_tegra_bo_open
drm_tegra_bo_ref
-drm_tegra_bo_set_flags
-drm_tegra_bo_set_tiling
drm_tegra_bo_unmap
drm_tegra_bo_unref
drm_tegra_bo_wrap
+drm_tegra_channel_close
+drm_tegra_channel_get_version
+drm_tegra_channel_map
+drm_tegra_channel_open
+drm_tegra_channel_unmap
drm_tegra_close
+drm_tegra_fence_wait
+drm_tegra_job_free
+drm_tegra_job_get_pushbuf
+drm_tegra_job_new
+drm_tegra_job_submit
+drm_tegra_job_wait
drm_tegra_new
+drm_tegra_pushbuf_begin
+drm_tegra_pushbuf_end
+drm_tegra_pushbuf_relocate
+drm_tegra_pushbuf_sync
+drm_tegra_pushbuf_sync_cond
+drm_tegra_pushbuf_wait
+drm_tegra_syncpoint_free
+drm_tegra_syncpoint_new
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tegra/tegra.c
^
|
| @@ -37,288 +37,318 @@
static void drm_tegra_bo_free(struct drm_tegra_bo *bo)
{
- struct drm_tegra *drm = bo->drm;
+ struct drm_tegra *drm = bo->drm;
- if (bo->map)
- munmap(bo->map, bo->size);
+ if (bo->map)
+ munmap(bo->map, bo->size);
- drmCloseBufferHandle(drm->fd, bo->handle);
+ drmCloseBufferHandle(drm->fd, bo->handle);
- free(bo);
+ free(bo);
}
static int drm_tegra_wrap(struct drm_tegra **drmp, int fd, bool close)
{
- struct drm_tegra *drm;
+ struct drm_tegra *drm;
- if (fd < 0 || !drmp)
- return -EINVAL;
+ if (fd < 0 || !drmp)
+ return -EINVAL;
- drm = calloc(1, sizeof(*drm));
- if (!drm)
- return -ENOMEM;
+ drm = calloc(1, sizeof(*drm));
+ if (!drm)
+ return -ENOMEM;
- drm->close = close;
- drm->fd = fd;
+ drm->close = close;
+ drm->fd = fd;
- *drmp = drm;
+ *drmp = drm;
- return 0;
+ return 0;
}
-drm_public int drm_tegra_new(struct drm_tegra **drmp, int fd)
+drm_public int drm_tegra_new(int fd, struct drm_tegra **drmp)
{
- bool supported = false;
- drmVersionPtr version;
+ bool supported = false;
+ drmVersionPtr version;
- version = drmGetVersion(fd);
- if (!version)
- return -ENOMEM;
+ version = drmGetVersion(fd);
+ if (!version)
+ return -ENOMEM;
- if (!strncmp(version->name, "tegra", version->name_len))
- supported = true;
+ if (!strncmp(version->name, "tegra", version->name_len))
+ supported = true;
- drmFreeVersion(version);
+ drmFreeVersion(version);
- if (!supported)
- return -ENOTSUP;
+ if (!supported)
+ return -ENOTSUP;
- return drm_tegra_wrap(drmp, fd, false);
+ return drm_tegra_wrap(drmp, fd, false);
}
drm_public void drm_tegra_close(struct drm_tegra *drm)
{
- if (!drm)
- return;
+ if (!drm)
+ return;
- if (drm->close)
- close(drm->fd);
+ if (drm->close)
+ close(drm->fd);
- free(drm);
+ free(drm);
}
-drm_public int drm_tegra_bo_new(struct drm_tegra_bo **bop, struct drm_tegra *drm,
- uint32_t flags, uint32_t size)
+static struct drm_tegra_bo *drm_tegra_bo_alloc(struct drm_tegra *drm,
+ uint32_t handle,
+ uint32_t flags,
+ uint32_t size)
{
- struct drm_tegra_gem_create args;
- struct drm_tegra_bo *bo;
- int err;
+ struct drm_tegra_bo *bo;
- if (!drm || size == 0 || !bop)
- return -EINVAL;
+ bo = calloc(1, sizeof(*bo));
+ if (!bo)
+ return NULL;
- bo = calloc(1, sizeof(*bo));
- if (!bo)
- return -ENOMEM;
+ atomic_set(&bo->ref, 1);
+ bo->handle = handle;
+ bo->flags = flags;
+ bo->size = size;
+ bo->drm = drm;
- atomic_set(&bo->ref, 1);
- bo->flags = flags;
- bo->size = size;
- bo->drm = drm;
+ return bo;
+}
+
+drm_public int
+drm_tegra_bo_new(struct drm_tegra *drm, uint32_t flags, uint32_t size,
+ struct drm_tegra_bo **bop)
+{
+ struct drm_tegra_gem_create args;
+ struct drm_tegra_bo *bo;
+ int err;
+
+ if (!drm || size == 0 || !bop)
+ return -EINVAL;
+
+ bo = drm_tegra_bo_alloc(drm, 0, flags, size);
+ if (!bo)
+ return -ENOMEM;
- memset(&args, 0, sizeof(args));
- args.flags = flags;
- args.size = size;
+ memset(&args, 0, sizeof(args));
+ args.flags = flags;
+ args.size = size;
- err = drmCommandWriteRead(drm->fd, DRM_TEGRA_GEM_CREATE, &args,
- sizeof(args));
- if (err < 0) {
- err = -errno;
- free(bo);
- return err;
- }
+ err = drmCommandWriteRead(drm->fd, DRM_TEGRA_GEM_CREATE, &args,
+ sizeof(args));
+ if (err < 0) {
+ err = -errno;
+ free(bo);
+ return err;
+ }
- bo->handle = args.handle;
+ bo->handle = args.handle;
- *bop = bo;
+ *bop = bo;
- return 0;
+ return 0;
}
-drm_public int drm_tegra_bo_wrap(struct drm_tegra_bo **bop, struct drm_tegra *drm,
- uint32_t handle, uint32_t flags, uint32_t size)
+drm_public int
+drm_tegra_bo_wrap(struct drm_tegra *drm, uint32_t handle, uint32_t flags,
+ uint32_t size, struct drm_tegra_bo **bop)
{
- struct drm_tegra_bo *bo;
+ struct drm_tegra_bo *bo;
- if (!drm || !bop)
- return -EINVAL;
+ if (!drm || !bop)
+ return -EINVAL;
- bo = calloc(1, sizeof(*bo));
- if (!bo)
- return -ENOMEM;
+ bo = drm_tegra_bo_alloc(drm, handle, flags, size);
+ if (!bo)
+ return -ENOMEM;
- atomic_set(&bo->ref, 1);
- bo->handle = handle;
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tegra/tegra.h
^
|
| @@ -28,33 +28,100 @@
#include <stdint.h>
#include <stdlib.h>
+#include <tegra_drm.h>
+
+enum drm_tegra_class {
+ DRM_TEGRA_HOST1X,
+ DRM_TEGRA_GR2D,
+ DRM_TEGRA_GR3D,
+ DRM_TEGRA_VIC,
+};
+
struct drm_tegra_bo;
struct drm_tegra;
-int drm_tegra_new(struct drm_tegra **drmp, int fd);
+int drm_tegra_new(int fd, struct drm_tegra **drmp);
void drm_tegra_close(struct drm_tegra *drm);
-int drm_tegra_bo_new(struct drm_tegra_bo **bop, struct drm_tegra *drm,
- uint32_t flags, uint32_t size);
-int drm_tegra_bo_wrap(struct drm_tegra_bo **bop, struct drm_tegra *drm,
- uint32_t handle, uint32_t flags, uint32_t size);
+int drm_tegra_bo_new(struct drm_tegra *drm, uint32_t flags, uint32_t size,
+ struct drm_tegra_bo **bop);
+int drm_tegra_bo_wrap(struct drm_tegra *drm, uint32_t handle, uint32_t flags,
+ uint32_t size, struct drm_tegra_bo **bop);
struct drm_tegra_bo *drm_tegra_bo_ref(struct drm_tegra_bo *bo);
void drm_tegra_bo_unref(struct drm_tegra_bo *bo);
int drm_tegra_bo_get_handle(struct drm_tegra_bo *bo, uint32_t *handle);
int drm_tegra_bo_map(struct drm_tegra_bo *bo, void **ptr);
int drm_tegra_bo_unmap(struct drm_tegra_bo *bo);
-int drm_tegra_bo_get_flags(struct drm_tegra_bo *bo, uint32_t *flags);
-int drm_tegra_bo_set_flags(struct drm_tegra_bo *bo, uint32_t flags);
-
-struct drm_tegra_bo_tiling {
- uint32_t mode;
- uint32_t value;
+int drm_tegra_bo_get_name(struct drm_tegra_bo *bo, uint32_t *name);
+int drm_tegra_bo_open(struct drm_tegra *drm, uint32_t name, uint32_t flags,
+ struct drm_tegra_bo **bop);
+
+int drm_tegra_bo_export(struct drm_tegra_bo *bo, uint32_t flags);
+int drm_tegra_bo_import(struct drm_tegra *drm, int fd,
+ struct drm_tegra_bo **bop);
+
+struct drm_tegra_channel;
+struct drm_tegra_mapping;
+struct drm_tegra_pushbuf;
+struct drm_tegra_job;
+struct drm_tegra_syncpoint;
+
+enum drm_tegra_sync_cond {
+ DRM_TEGRA_SYNC_COND_IMMEDIATE,
+ DRM_TEGRA_SYNC_COND_OP_DONE,
+ DRM_TEGRA_SYNC_COND_RD_DONE,
+ DRM_TEGRA_SYNC_COND_WR_SAFE,
+ DRM_TEGRA_SYNC_COND_MAX,
+ };
+
+struct drm_tegra_fence {
+ struct drm_tegra *drm;
+ uint32_t syncpt;
+ uint32_t value;
};
-int drm_tegra_bo_get_tiling(struct drm_tegra_bo *bo,
- struct drm_tegra_bo_tiling *tiling);
-int drm_tegra_bo_set_tiling(struct drm_tegra_bo *bo,
- const struct drm_tegra_bo_tiling *tiling);
+int drm_tegra_channel_open(struct drm_tegra *drm,
+ enum drm_tegra_class client,
+ struct drm_tegra_channel **channelp);
+int drm_tegra_channel_close(struct drm_tegra_channel *channel);
+unsigned int drm_tegra_channel_get_version(struct drm_tegra_channel *channel);
+int drm_tegra_channel_map(struct drm_tegra_channel *channel,
+ struct drm_tegra_bo *bo, uint32_t flags,
+ struct drm_tegra_mapping **mapp);
+int drm_tegra_channel_unmap(struct drm_tegra_mapping *map);
+
+int drm_tegra_job_new(struct drm_tegra_channel *channel,
+ struct drm_tegra_job **jobp);
+int drm_tegra_job_free(struct drm_tegra_job *job);
+int drm_tegra_job_get_pushbuf(struct drm_tegra_job *job,
+ struct drm_tegra_pushbuf **pushbufp);
+int drm_tegra_job_submit(struct drm_tegra_job *job,
+ struct drm_tegra_fence *fence);
+int drm_tegra_job_wait(struct drm_tegra_job *job, unsigned long timeout);
+
+int drm_tegra_pushbuf_begin(struct drm_tegra_pushbuf *pushbuf,
+ unsigned int words, uint32_t **ptrp);
+int drm_tegra_pushbuf_end(struct drm_tegra_pushbuf *pushbuf, uint32_t *ptr);
+int drm_tegra_pushbuf_wait(struct drm_tegra_pushbuf *pushbuf,
+ struct drm_tegra_syncpoint *syncpt,
+ uint32_t value);
+int drm_tegra_pushbuf_relocate(struct drm_tegra_pushbuf *pushbuf,
+ uint32_t **ptrp,
+ struct drm_tegra_mapping *target,
+ unsigned long offset, unsigned int shift,
+ uint32_t flags);
+int drm_tegra_pushbuf_sync(struct drm_tegra_pushbuf *pushbuf,
+ struct drm_tegra_syncpoint *syncpt,
+ unsigned int count);
+int drm_tegra_pushbuf_sync_cond(struct drm_tegra_pushbuf *pushbuf,
+ uint32_t **ptrp,
+ struct drm_tegra_syncpoint *syncpt,
+ enum drm_tegra_sync_cond cond);
+
+int drm_tegra_syncpoint_new(struct drm_tegra *drm,
+ struct drm_tegra_syncpoint **syncptp);
+int drm_tegra_syncpoint_free(struct drm_tegra_syncpoint *syncpt);
+int drm_tegra_fence_wait(struct drm_tegra_fence *fence, unsigned long timeout);
#endif /* __DRM_TEGRA_H__ */
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/amdgpu/amdgpu_test.c
^
|
| @@ -73,6 +73,7 @@
#define SYNCOBJ_TIMELINE_TESTS_STR "SYNCOBJ TIMELINE Tests"
#define SECURITY_TESTS_STR "Security Tests"
#define HOTUNPLUG_TESTS_STR "Hotunplug Tests"
+#define CP_DMA_TESTS_STR "CP DMA Tests"
/**
* Open handles for amdgpu devices
@@ -163,6 +164,12 @@
.pCleanupFunc = suite_hotunplug_tests_clean,
.pTests = hotunplug_tests,
},
+ {
+ .pName = CP_DMA_TESTS_STR,
+ .pInitFunc = suite_cp_dma_tests_init,
+ .pCleanupFunc = suite_cp_dma_tests_clean,
+ .pTests = cp_dma_tests,
+ },
CU_SUITE_INFO_NULL,
};
@@ -232,6 +239,10 @@
.pName = HOTUNPLUG_TESTS_STR,
.pActive = suite_hotunplug_tests_enable,
},
+ {
+ .pName = CP_DMA_TESTS_STR,
+ .pActive = suite_cp_dma_tests_enable,
+ },
};
@@ -311,6 +322,10 @@
int fd;
drmVersionPtr version;
+ for (i = 0; i < MAX_CARDS_SUPPORTED; i++) {
+ drm_amdgpu[i] = -1;
+ }
+
drm_count = drmGetDevices2(0, devices, MAX_CARDS_SUPPORTED);
if (drm_count < 0) {
@@ -534,6 +549,14 @@
"gfx ring slow bad draw test (set amdgpu.lockup_timeout=50)", CU_FALSE))
fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
+ if (amdgpu_set_test_active(DEADLOCK_TESTS_STR,
+ "sdma ring corrupted header test (set amdgpu.lockup_timeout=50)", CU_FALSE))
+ fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
+
+ if (amdgpu_set_test_active(DEADLOCK_TESTS_STR,
+ "sdma ring slow linear copy test (set amdgpu.lockup_timeout=50)", CU_FALSE))
+ fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
+
if (amdgpu_set_test_active(BASIC_TESTS_STR, "bo eviction Test", CU_FALSE))
fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/amdgpu/amdgpu_test.h
^
|
| @@ -261,11 +261,26 @@
*/
extern CU_TestInfo syncobj_timeline_tests[];
-void amdgpu_dispatch_hang_helper(amdgpu_device_handle device_handle, uint32_t ip_type);
-void amdgpu_dispatch_hang_slow_helper(amdgpu_device_handle device_handle, uint32_t ip_type);
-void amdgpu_memcpy_draw_test(amdgpu_device_handle device_handle, uint32_t ring,
- int hang);
-void amdgpu_memcpy_draw_hang_slow_test(amdgpu_device_handle device_handle, uint32_t ring);
+
+/**
+ * Initialize cp dma test suite
+ */
+int suite_cp_dma_tests_init();
+
+/**
+ * Deinitialize cp dma test suite
+ */
+int suite_cp_dma_tests_clean();
+
+/**
+ * Decide if the suite is enabled by default or not.
+ */
+CU_BOOL suite_cp_dma_tests_enable(void);
+
+/**
+ * Tests in cp dma test suite
+ */
+extern CU_TestInfo cp_dma_tests[];
/**
* Initialize security test suite
@@ -293,7 +308,12 @@
unsigned ip_type,
bool secure);
-
+extern void amdgpu_test_dispatch_helper(amdgpu_device_handle device_handle, unsigned ip);
+extern void amdgpu_test_dispatch_hang_helper(amdgpu_device_handle device_handle, uint32_t ip);
+extern void amdgpu_test_dispatch_hang_slow_helper(amdgpu_device_handle device_handle, uint32_t ip);
+extern void amdgpu_test_draw_helper(amdgpu_device_handle device_handle);
+extern void amdgpu_test_draw_hang_helper(amdgpu_device_handle device_handle);
+extern void amdgpu_test_draw_hang_slow_helper(amdgpu_device_handle device_handle);
/**
* Initialize hotunplug test suite
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/amdgpu/basic_tests.c
^
|
| @@ -292,6 +292,8 @@
#define PKT3_SET_SH_REG 0x76
#define PACKET3_SET_SH_REG_START 0x00002c00
+#define PKT3_SET_SH_REG_INDEX 0x9B
+
#define PACKET3_DISPATCH_DIRECT 0x15
#define PACKET3_EVENT_WRITE 0x46
#define PACKET3_ACQUIRE_MEM 0x58
@@ -351,6 +353,12 @@
0xbf810000
};
+static const uint32_t bufferclear_cs_shader_gfx10[] = {
+ 0xD7460004, 0x04010C08, 0x7E000204, 0x7E020205,
+ 0x7E040206, 0x7E060207, 0xE01C2000, 0x80000004,
+ 0xBF810000
+};
+
static const uint32_t bufferclear_cs_shader_registers_gfx9[][2] = {
{0x2e12, 0x000C0041}, //{ mmCOMPUTE_PGM_RSRC1, 0x000C0041 },
{0x2e13, 0x00000090}, //{ mmCOMPUTE_PGM_RSRC2, 0x00000090 },
@@ -367,6 +375,11 @@
0xe01c2000, 0x80010200, 0xbf810000
};
+static const uint32_t buffercopy_cs_shader_gfx10[] = {
+ 0xD7460001, 0x04010C08, 0xE00C2000, 0x80000201,
+ 0xBF8C3F70, 0xE01C2000, 0x80010201, 0xBF810000
+};
+
static const uint32_t preamblecache_gfx9[] = {
0xc0026900, 0x81, 0x80000000, 0x40004000, 0xc0026900, 0x8c, 0xaa99aaaa, 0x0,
0xc0026900, 0x90, 0x80000000, 0x40004000, 0xc0026900, 0x94, 0x80000000, 0x40004000,
@@ -390,6 +403,32 @@
0xc0017900, 0x24b, 0x0
};
+static const uint32_t preamblecache_gfx10[] = {
+ 0xc0026900, 0x81, 0x80000000, 0x40004000, 0xc0026900, 0x8c, 0xaa99aaaa, 0x0,
+ 0xc0026900, 0x90, 0x80000000, 0x40004000, 0xc0026900, 0x94, 0x80000000, 0x40004000,
+ 0xc0026900, 0xb4, 0x0, 0x3f800000, 0xc0016900, 0x103, 0x0,
+ 0xc0016900, 0x208, 0x0, 0xc0016900, 0x290, 0x0,
+ 0xc0016900, 0x2a1, 0x0, 0xc0026900, 0x2ad, 0x0, 0x0,
+ 0xc0016900, 0x2d5, 0x10000, 0xc0016900, 0x2dc, 0x0,
+ 0xc0066900, 0x2de, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc0026900, 0x2e5, 0x0, 0x0,
+ 0xc0056900, 0x2f9, 0x5, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
+ 0xc0046900, 0x310, 0, 0x3, 0, 0x100000, 0xc0026900, 0x316, 0xe, 0x20,
+ 0xc0016900, 0x349, 0x0, 0xc0016900, 0x358, 0x0, 0xc0016900, 0x367, 0x0,
+ 0xc0016900, 0x376, 0x0, 0xc0016900, 0x385, 0x0, 0xc0016900, 0x6, 0x0,
+ 0xc0056900, 0xe8, 0x0, 0x0, 0x0, 0x0, 0x0,
+ 0xc0076900, 0x1e1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+ 0xc0026900, 0x204, 0x90000, 0x4, 0xc0046900, 0x20c, 0x0, 0x0, 0x0, 0x0,
+ 0xc0016900, 0x2b2, 0x0, 0xc0026900, 0x30e, 0xffffffff, 0xffffffff,
+ 0xc0016900, 0x314, 0x0, 0xc0016900, 0x10a, 0, 0xc0016900, 0x2a6, 0, 0xc0016900, 0x210, 0,
+ 0xc0016900, 0x2db, 0, 0xc0016900, 0x1d4, 0, 0xc0002f00, 0x1, 0xc0016900, 0x1, 0x1, 0xc0016900, 0xe, 0x2,
+ 0xc0016900, 0x206, 0x300, 0xc0016900, 0x212, 0x200, 0xc0017900, 0x7b, 0x20, 0xc0017a00, 0x20000243, 0x0,
+ 0xc0017900, 0x249, 0, 0xc0017900, 0x24a, 0, 0xc0017900, 0x24b, 0, 0xc0017900, 0x259, 0xffffffff,
+ 0xc0017900, 0x25f, 0, 0xc0017900, 0x260, 0, 0xc0017900, 0x262, 0,
+ 0xc0017600, 0x45, 0x0, 0xc0017600, 0x6, 0x0,
+ 0xc0067600, 0x70, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+ 0xc0067600, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
+};
+
enum ps_type {
PS_CONST,
PS_TEX,
@@ -442,6 +481,39 @@
{0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 }
};
+static const uint32_t ps_const_shader_gfx10[] = {
+ 0x7E000200, 0x7E020201, 0x7E040202, 0x7E060203,
+ 0x5E000300, 0x5E020702, 0xBF800000, 0xBF800000,
+ 0xF8001C0F, 0x00000100, 0xBF810000
+};
+
+static const uint32_t ps_const_shader_patchinfo_code_size_gfx10 = 6;
+
+static const uint32_t ps_const_shader_patchinfo_code_gfx10[][10][6] = {
+ {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001890, 0x00000000 },
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001801, 0x00000000 },
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001803, 0x00000100 },
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001803, 0x00000300 },
+ { 0x5E000300, 0x5E020702, 0xBF800000, 0xBF800000, 0xF8001C0F, 0x00000100 },
+ { 0xD7690000, 0x00020300, 0xD7690001, 0x00020702, 0xF8001C0F, 0x00000100 },
+ { 0xD7680000, 0x00020300, 0xD7680001, 0x00020702, 0xF8001C0F, 0x00000100 },
+ { 0xD76A0000, 0x00020300, 0xD76A0001, 0x00020702, 0xF8001C0F, 0x00000100 },
+ { 0xD76B0000, 0x00020300, 0xD76B0001, 0x00020702, 0xF8001C0F, 0x00000100 },
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF800180F, 0x03020100 }
+ }
+};
+
+static const uint32_t ps_const_shader_patchinfo_offset_gfx10[] = {
+ 0x00000004
+};
+
+static const uint32_t ps_num_sh_registers_gfx10 = 2;
+
+static const uint32_t ps_const_sh_registers_gfx10[][2] = {
+ {0x2C0A, 0x000C0000},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0000 },
+ {0x2C0B, 0x00000008}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000008 }
+};
+
static const uint32_t ps_tex_shader_gfx9[] = {
0xBEFC000C, 0xBE8E017E, 0xBEFE077E, 0xD4180000,
0xD4190001, 0xD41C0100, 0xD41D0101, 0xF0800F00,
@@ -485,6 +557,34 @@
{0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 }
};
+static const uint32_t ps_tex_shader_gfx10[] = {
+ 0xBEFC030C, 0xBE8E047E, 0xBEFE0A7E, 0xC8080000,
+ 0xC80C0100, 0xC8090001, 0xC80D0101, 0xF0800F0A,
+ 0x00400402, 0x00000003, 0xBEFE040E, 0xBF8C0F70,
+ 0x5E000B04, 0x5E020F06, 0xBF800000, 0xBF800000,
+ 0xF8001C0F, 0x00000100, 0xBF810000
+};
+
+static const uint32_t ps_tex_shader_patchinfo_offset_gfx10[] = {
+ 0x0000000C
+};
+
+static const uint32_t ps_tex_shader_patchinfo_code_size_gfx10 = 6;
+
+static const uint32_t ps_tex_shader_patchinfo_code_gfx10[][10][6] = {
+ {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001890, 0x00000000 },
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001801, 0x00000004 },
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001803, 0x00000504 },
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001803, 0x00000704 },
+ { 0x5E000B04, 0x5E020F06, 0xBF800000, 0xBF800000, 0xF8001C0F, 0x00000100 },
+ { 0xD7690000, 0x00020B04, 0xD7690001, 0x00020F06, 0xF8001C0F, 0x00000100 },
+ { 0xD7680000, 0x00020B04, 0xD7680001, 0x00020F06, 0xF8001C0F, 0x00000100 },
+ { 0xD76A0000, 0x00020B04, 0xD76A0001, 0x00020F06, 0xF8001C0F, 0x00000100 },
+ { 0xD76B0000, 0x00020B04, 0xD76B0001, 0x00020F06, 0xF8001C0F, 0x00000100 },
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF800180F, 0x07060504 }
+ }
+};
+
static const uint32_t vs_RectPosTexFast_shader_gfx9[] = {
0x7E000B00, 0x020000F3, 0xD042000A, 0x00010100,
0x7E020202, 0x7E040200, 0x020000F3, 0x7E060206,
@@ -496,6 +596,17 @@
0xC400020F, 0x05060403, 0xBF810000
};
+static const uint32_t vs_RectPosTexFast_shader_gfx10[] = {
+ 0x7E000B00, 0x060000F3, 0x7E020202, 0x7E040206,
+ 0x7C040080, 0x060000F3, 0xD5010001, 0x01AA0200,
+ 0x7E060203, 0xD5010002, 0x01AA0404, 0x7E080207,
+ 0x7C040080, 0xD5010000, 0x01A80101, 0xD5010001,
+ 0x01AA0601, 0x7E060208, 0x7E0A02F2, 0xD5010002,
+ 0x01A80902, 0xD5010004, 0x01AA0805, 0x7E0C0209,
+ 0xF80008CF, 0x05030100, 0xF800020F, 0x05060402,
+ 0xBF810000
+};
+
static const uint32_t cached_cmd_gfx9[] = {
0xc0016900, 0x0, 0x0, 0xc0026900, 0x3, 0x2a, 0x0,
0xc0046900, 0xa, 0x0, 0x0, 0x0, 0x200020,
@@ -507,6 +618,17 @@
0xc0026900, 0x2b0, 0x0, 0x0, 0xc0016900, 0x2f8, 0x0
};
+static const uint32_t cached_cmd_gfx10[] = {
+ 0xc0016900, 0x0, 0x0, 0xc0026900, 0x3, 0x2a, 0x0,
+ 0xc0046900, 0xa, 0x0, 0x0, 0x0, 0x200020,
+ 0xc0016900, 0x83, 0xffff, 0xc0026900, 0x8e, 0xf, 0xf,
+ 0xc0056900, 0x105, 0x0, 0x0, 0x0, 0x0, 0x18,
+ 0xc0026900, 0x10b, 0x0, 0x0, 0xc0016900, 0x1e0, 0x0,
+ 0xc0036900, 0x200, 0x0, 0x10000, 0xcc0011,
+ 0xc0026900, 0x292, 0x20, 0x6020000,
+ 0xc0026900, 0x2b0, 0x0, 0x0, 0xc0016900, 0x2f8, 0x0
+};
+
unsigned int memcpy_ps_hang[] = {
0xFFFFFFFF, 0xBEFE0A7E, 0xBEFC0304, 0xC0C20100,
0xC0800300, 0xC8080000, 0xC80C0100, 0xC8090001,
@@ -546,6 +668,18 @@
1
};
+unsigned int memcpy_cs_hang_slow_nv_codes[] = {
+ 0xd7460000, 0x04010c08, 0xe00c2000, 0x80000100,
+ 0xbf8c0f70, 0xe01ca000, 0x80010100, 0xbf810000
+};
+
+struct amdgpu_test_shader memcpy_cs_hang_slow_nv = {
+ memcpy_cs_hang_slow_nv_codes,
+ 4,
+ 3,
+ 1
+};
+
unsigned int memcpy_ps_hang_slow_ai_codes[] = {
0xbefc000c, 0xbe8e017e, 0xbefe077e, 0xd4080000,
0xd4090001, 0xd40c0100, 0xd40d0101, 0xf0800f00,
@@ -723,6 +857,13 @@
amdgpu_bo_list_handle bo_list;
amdgpu_va_handle va_handle, va_handle_ce;
|
|
[-]
[+]
|
Added |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/amdgpu/cp_dma_tests.c
^
|
| @@ -0,0 +1,533 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+*/
+
+#include <unistd.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <inttypes.h>
+
+#include "CUnit/Basic.h"
+
+#include "amdgpu_test.h"
+#include "amdgpu_drm.h"
+#include "amdgpu_internal.h"
+
+#define IB_SIZE 4096
+#define MAX_RESOURCES 8
+
+#define DMA_SIZE 4097
+#define DMA_DATA_BYTE 0xea
+
+static bool do_p2p;
+
+static amdgpu_device_handle executing_device_handle;
+static uint32_t executing_device_major_version;
+static uint32_t executing_device_minor_version;
+
+static amdgpu_device_handle peer_exporting_device_handle;
+static uint32_t peer_exporting_device_major_version;
+static uint32_t peer_exporting_device_minor_version;
+
+static amdgpu_context_handle context_handle;
+static amdgpu_bo_handle ib_handle;
+static uint32_t *ib_cpu;
+static uint64_t ib_mc_address;
+static amdgpu_va_handle ib_va_handle;
+static uint32_t num_dword;
+
+static amdgpu_bo_handle resources[MAX_RESOURCES];
+static unsigned num_resources;
+
+static uint8_t* reference_data;
+
+static void amdgpu_cp_dma_host_to_vram(void);
+static void amdgpu_cp_dma_vram_to_host(void);
+static void amdgpu_cp_dma_p2p_vram_to_vram(void);
+static void amdgpu_cp_dma_p2p_host_to_vram(void);
+static void amdgpu_cp_dma_p2p_vram_to_host(void);
+
+/**
+ * Tests in cp dma test suite
+ */
+CU_TestInfo cp_dma_tests[] = {
+ { "CP DMA write Host to VRAM", amdgpu_cp_dma_host_to_vram },
+ { "CP DMA write VRAM to Host", amdgpu_cp_dma_vram_to_host },
+
+ { "Peer to Peer CP DMA write VRAM to VRAM", amdgpu_cp_dma_p2p_vram_to_vram },
+ { "Peer to Peer CP DMA write Host to VRAM", amdgpu_cp_dma_p2p_host_to_vram },
+ { "Peer to Peer CP DMA write VRAM to Host", amdgpu_cp_dma_p2p_vram_to_host },
+ CU_TEST_INFO_NULL,
+};
+
+struct amdgpu_cp_dma_bo{
+ amdgpu_bo_handle buf_handle;
+ amdgpu_va_handle va_handle;
+ uint64_t gpu_va;
+ uint64_t size;
+};
+
+static int allocate_bo_and_va(amdgpu_device_handle dev,
+ uint64_t size, uint64_t alignment,
+ uint32_t heap, uint64_t alloc_flags,
+ struct amdgpu_cp_dma_bo *bo) {
+ struct amdgpu_bo_alloc_request request = {};
+ amdgpu_bo_handle buf_handle;
+ amdgpu_va_handle va_handle;
+ uint64_t vmc_addr;
+ int r;
+
+ request.alloc_size = size;
+ request.phys_alignment = alignment;
+ request.preferred_heap = heap;
+ request.flags = alloc_flags;
+
+ r = amdgpu_bo_alloc(dev, &request, &buf_handle);
+ if (r)
+ goto error_bo_alloc;
+
+ r = amdgpu_va_range_alloc(dev, amdgpu_gpu_va_range_general,
+ size, alignment, 0,
+ &vmc_addr, &va_handle, 0);
+ if (r)
+ goto error_va_alloc;
+
+ r = amdgpu_bo_va_op(buf_handle, 0, size, vmc_addr,
+ AMDGPU_VM_PAGE_READABLE |
+ AMDGPU_VM_PAGE_WRITEABLE |
+ AMDGPU_VM_PAGE_EXECUTABLE,
+ AMDGPU_VA_OP_MAP);
+ if (r)
+ goto error_va_map;
+
+ bo->buf_handle = buf_handle;
+ bo->va_handle = va_handle;
+ bo->gpu_va = vmc_addr;
+ bo->size = size;
+
+ return 0;
+
+error_va_map:
+ amdgpu_bo_va_op(buf_handle, 0,
+ size, vmc_addr, 0, AMDGPU_VA_OP_UNMAP);
+
+error_va_alloc:
+ amdgpu_va_range_free(va_handle);
+
+error_bo_alloc:
+ amdgpu_bo_free(buf_handle);
+
+ return r;
+}
+
+static int import_dma_buf_to_bo(amdgpu_device_handle dev,
+ int dmabuf_fd, struct amdgpu_cp_dma_bo *bo) {
+ amdgpu_va_handle va_handle;
+ uint64_t vmc_addr;
+ int r;
+ struct amdgpu_bo_import_result bo_import_result = {};
+
+ r = amdgpu_bo_import(dev, amdgpu_bo_handle_type_dma_buf_fd,
+ dmabuf_fd, &bo_import_result);
+ if (r)
+ goto error_bo_import;
+
+ r = amdgpu_va_range_alloc(dev, amdgpu_gpu_va_range_general,
+ bo_import_result.alloc_size, 0, 0,
+ &vmc_addr, &va_handle, 0);
+ if (r)
+ goto error_va_alloc;
+
+ r = amdgpu_bo_va_op(bo_import_result.buf_handle, 0,
+ bo_import_result.alloc_size, vmc_addr,
+ AMDGPU_VM_PAGE_READABLE |
+ AMDGPU_VM_PAGE_WRITEABLE |
+ AMDGPU_VM_PAGE_EXECUTABLE,
+ AMDGPU_VA_OP_MAP);
+ if (r)
+ goto error_va_map;
+
+ bo->buf_handle = bo_import_result.buf_handle;
+ bo->va_handle = va_handle;
+ bo->gpu_va = vmc_addr;
+ bo->size = bo_import_result.alloc_size;
+
+ return 0;
+
+error_va_map:
+ amdgpu_bo_va_op(bo_import_result.buf_handle, 0,
+ bo_import_result.alloc_size, vmc_addr, 0, AMDGPU_VA_OP_UNMAP);
+
+error_va_alloc:
+ amdgpu_va_range_free(va_handle);
+
+error_bo_import:
+ amdgpu_bo_free(bo_import_result.buf_handle);
+
+ return r;
+}
+
+static int free_bo(struct amdgpu_cp_dma_bo bo) {
+ int r;
+ r = amdgpu_bo_va_op(bo.buf_handle, 0,
+ bo.size, bo.gpu_va, 0, AMDGPU_VA_OP_UNMAP);
+ if(r)
+ return r;
+
+ r = amdgpu_va_range_free(bo.va_handle);
+ if(r)
+ return r;
+
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/amdgpu/deadlock_tests.c
^
|
| @@ -124,6 +124,8 @@
static void amdgpu_dispatch_hang_slow_compute(void);
static void amdgpu_draw_hang_gfx(void);
static void amdgpu_draw_hang_slow_gfx(void);
+static void amdgpu_hang_sdma(void);
+static void amdgpu_hang_slow_sdma(void);
CU_BOOL suite_deadlock_tests_enable(void)
{
@@ -139,11 +141,13 @@
/*
* Only enable for ASICs supporting GPU reset and for which it's enabled
- * by default (currently GFX8/9 dGPUS)
+ * by default (currently GFX8+ dGPUS and gfx9+ APUs). Note that Raven1
+ * did not support GPU reset, but newer variants do.
*/
- if (family_id != AMDGPU_FAMILY_VI &&
- family_id != AMDGPU_FAMILY_AI &&
- family_id != AMDGPU_FAMILY_CI) {
+ if (family_id == AMDGPU_FAMILY_SI ||
+ family_id == AMDGPU_FAMILY_KV ||
+ family_id == AMDGPU_FAMILY_CZ ||
+ family_id == AMDGPU_FAMILY_RV) {
printf("\n\nGPU reset is not enabled for the ASIC, deadlock suite disabled\n");
enable = CU_FALSE;
}
@@ -206,6 +210,8 @@
{ "compute ring bad slow dispatch test (set amdgpu.lockup_timeout=50,50)", amdgpu_dispatch_hang_slow_compute },
{ "gfx ring bad draw test (set amdgpu.lockup_timeout=50)", amdgpu_draw_hang_gfx },
{ "gfx ring slow bad draw test (set amdgpu.lockup_timeout=50)", amdgpu_draw_hang_slow_gfx },
+ { "sdma ring corrupted header test (set amdgpu.lockup_timeout=50)", amdgpu_hang_sdma },
+ { "sdma ring slow linear copy test (set amdgpu.lockup_timeout=50)", amdgpu_hang_slow_sdma },
CU_TEST_INFO_NULL,
};
@@ -509,54 +515,182 @@
static void amdgpu_dispatch_hang_gfx(void)
{
- amdgpu_dispatch_hang_helper(device_handle, AMDGPU_HW_IP_GFX);
+ amdgpu_test_dispatch_hang_helper(device_handle, AMDGPU_HW_IP_GFX);
}
-
static void amdgpu_dispatch_hang_compute(void)
{
- amdgpu_dispatch_hang_helper(device_handle, AMDGPU_HW_IP_COMPUTE);
+ amdgpu_test_dispatch_hang_helper(device_handle, AMDGPU_HW_IP_COMPUTE);
}
-
static void amdgpu_dispatch_hang_slow_gfx(void)
{
- amdgpu_dispatch_hang_slow_helper(device_handle, AMDGPU_HW_IP_GFX);
+ amdgpu_test_dispatch_hang_slow_helper(device_handle, AMDGPU_HW_IP_GFX);
}
-
static void amdgpu_dispatch_hang_slow_compute(void)
{
- amdgpu_dispatch_hang_slow_helper(device_handle, AMDGPU_HW_IP_COMPUTE);
+ amdgpu_test_dispatch_hang_slow_helper(device_handle, AMDGPU_HW_IP_COMPUTE);
}
-
static void amdgpu_draw_hang_gfx(void)
{
- int r;
- struct drm_amdgpu_info_hw_ip info;
- uint32_t ring_id;
+ amdgpu_test_draw_hang_helper(device_handle);
+}
+static void amdgpu_draw_hang_slow_gfx(void)
+{
+ amdgpu_test_draw_hang_slow_helper(device_handle);
+}
- r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_GFX, 0, &info);
+#define DMA_CORRUPTED_HEADER_HANG 1
+#define DMA_SLOW_LINEARCOPY_HANG 2
+
+static void amdgpu_hang_sdma_helper(unsigned hang_type)
+{
+ const int sdma_write_length = 1024;
+ amdgpu_context_handle context_handle;
+ amdgpu_bo_handle ib_result_handle;
+ amdgpu_bo_handle bo1, bo2;
+ amdgpu_bo_handle resources[3];
+ amdgpu_bo_list_handle bo_list;
+ void *ib_result_cpu;
+ struct amdgpu_cs_ib_info ib_info;
+ struct amdgpu_cs_request ibs_request;
+ struct amdgpu_cs_fence fence_status;
+ uint64_t bo1_mc, bo2_mc;
+ uint64_t ib_result_mc_address;
+ volatile unsigned char *bo1_cpu, *bo2_cpu;
+ amdgpu_va_handle bo1_va_handle, bo2_va_handle;
+ amdgpu_va_handle va_handle;
+ struct drm_amdgpu_info_hw_ip hw_ip_info;
+ int i, j, r;
+ uint32_t expired, ib_size;
+
+ r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_DMA, 0, &hw_ip_info);
CU_ASSERT_EQUAL(r, 0);
- if (!info.available_rings)
- printf("SKIP ... as there's no graphic ring\n");
- for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
- amdgpu_memcpy_draw_test(device_handle, ring_id, 0);
- amdgpu_memcpy_draw_test(device_handle, ring_id, 1);
- amdgpu_memcpy_draw_test(device_handle, ring_id, 0);
- }
-}
+ r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+ CU_ASSERT_EQUAL(r, 0);
-static void amdgpu_draw_hang_slow_gfx(void)
-{
- struct drm_amdgpu_info_hw_ip info;
- uint32_t ring_id;
- int r;
+ if (hang_type == DMA_CORRUPTED_HEADER_HANG)
+ ib_size = 4096;
+ else
+ ib_size = 4096 * 0x20000;
- r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_GFX, 0, &info);
+ r = amdgpu_bo_alloc_and_map(device_handle, ib_size, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0,
+ &ib_result_handle, &ib_result_cpu,
+ &ib_result_mc_address, &va_handle);
CU_ASSERT_EQUAL(r, 0);
- for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
- amdgpu_memcpy_draw_test(device_handle, ring_id, 0);
- amdgpu_memcpy_draw_hang_slow_test(device_handle, ring_id);
- amdgpu_memcpy_draw_test(device_handle, ring_id, 0);
+ r = amdgpu_bo_alloc_and_map(device_handle,
+ sdma_write_length, 4096,
+ AMDGPU_GEM_DOMAIN_GTT,
+ 0, &bo1,
+ (void**)&bo1_cpu, &bo1_mc,
+ &bo1_va_handle);
+ CU_ASSERT_EQUAL(r, 0);
+
+ /* set bo1 */
+ memset((void*)bo1_cpu, 0xaa, sdma_write_length);
+
+ /* allocate UC bo2 for sDMA use */
+ r = amdgpu_bo_alloc_and_map(device_handle,
+ sdma_write_length, 4096,
+ AMDGPU_GEM_DOMAIN_GTT,
+ 0, &bo2,
+ (void**)&bo2_cpu, &bo2_mc,
+ &bo2_va_handle);
+ CU_ASSERT_EQUAL(r, 0);
+
+ /* clear bo2 */
+ memset((void*)bo2_cpu, 0, sdma_write_length);
+
+ resources[0] = bo1;
+ resources[1] = bo2;
+ resources[2] = ib_result_handle;
+ r = amdgpu_bo_list_create(device_handle, 3,
+ resources, NULL, &bo_list);
+
+ /* fulfill PM4: with bad copy linear header */
+ ptr = ib_result_cpu;
+ i = 0;
+ if (hang_type == DMA_CORRUPTED_HEADER_HANG) {
+ ptr[i++] = 0x23decd3d;
+ ptr[i++] = sdma_write_length - 1;
+ ptr[i++] = 0;
+ ptr[i++] = 0xffffffff & bo1_mc;
+ ptr[i++] = (0xffffffff00000000 & bo1_mc) >> 32;
+ ptr[i++] = 0xffffffff & bo2_mc;
+ ptr[i++] = (0xffffffff00000000 & bo2_mc) >> 32;
+ } else {
+ for (j = 1; j < 0x20000; j++) {
+ ptr[i++] = 0x1;
+ ptr[i++] = sdma_write_length - 1;
+ ptr[i++] = 0;
+ ptr[i++] = 0xffffffff & bo1_mc;
+ ptr[i++] = (0xffffffff00000000 & bo1_mc) >> 32;
+ ptr[i++] = 0xffffffff & bo2_mc;
+ ptr[i++] = (0xffffffff00000000 & bo2_mc) >> 32;
+ ptr[i++] = 0x1;
+ ptr[i++] = sdma_write_length - 1;
+ ptr[i++] = 0;
+ ptr[i++] = 0xffffffff & bo2_mc;
+ ptr[i++] = (0xffffffff00000000 & bo2_mc) >> 32;
+ ptr[i++] = 0xffffffff & bo1_mc;
+ ptr[i++] = (0xffffffff00000000 & bo1_mc) >> 32;
+ }
}
+
+ /* exec command */
+ memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info));
+ ib_info.ib_mc_address = ib_result_mc_address;
+ ib_info.size = i;
+
+ memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
+ ibs_request.ip_type = AMDGPU_HW_IP_DMA;
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/amdgpu/hotunplug_tests.c
^
|
| @@ -62,15 +62,13 @@
return CU_FALSE;
}
- /* Disable until the hot-unplug support in kernel gets into drm-next */
- if (major_version < 0xff)
- enable = false;
-
if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
&minor_version, &device_handle))
return CU_FALSE;
-
- /* TODO Once DRM version for unplug feature ready compare here agains it*/
+
+ /* Latest tested amdgpu version to work with all the tests */
+ if (minor_version < 46)
+ enable = false;
if (amdgpu_device_deinitialize(device_handle))
return CU_FALSE;
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/amdgpu/jpeg_tests.c
^
|
| @@ -179,12 +179,9 @@
return CU_FALSE;
}
- if (family_id == AMDGPU_FAMILY_RV) {
- if (chip_id >= (chip_rev + 0x91))
- jpeg_direct_reg = true;
- else
- jpeg_direct_reg = false;
- } else if (family_id == AMDGPU_FAMILY_NV)
+ if (info.hw_ip_version_major == 1)
+ jpeg_direct_reg = false;
+ else if (info.hw_ip_version_major > 1 && info.hw_ip_version_major <= 4)
jpeg_direct_reg = true;
else
return CU_FALSE;
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/amdgpu/meson.build
^
|
| @@ -25,7 +25,7 @@
'amdgpu_test.c', 'basic_tests.c', 'bo_tests.c', 'cs_tests.c',
'vce_tests.c', 'uvd_enc_tests.c', 'vcn_tests.c', 'deadlock_tests.c',
'vm_tests.c', 'ras_tests.c', 'syncobj_tests.c', 'security_tests.c',
- 'hotunplug_tests.c', 'jpeg_tests.c'
+ 'hotunplug_tests.c', 'jpeg_tests.c', 'cp_dma_tests.c', 'shader_test_util.c'
),
dependencies : [dep_cunit, dep_threads, dep_atomic_ops],
include_directories : [inc_root, inc_drm, include_directories('../../amdgpu')],
|
|
[-]
[+]
|
Added |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/amdgpu/shader_code.h
^
|
| @@ -0,0 +1,153 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+*/
+
+#ifndef _shader_code_h_
+#define _shader_code_h_
+
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
+#endif
+
+enum amdgpu_test_gfx_version {
+ AMDGPU_TEST_GFX_V9 = 0,
+ AMDGPU_TEST_GFX_V10,
+ AMDGPU_TEST_GFX_V11,
+ AMDGPU_TEST_GFX_MAX,
+};
+
+enum cs_type {
+ CS_BUFFERCLEAR = 0,
+ CS_BUFFERCOPY,
+ CS_HANG,
+ CS_HANG_SLOW,
+};
+
+enum ps_type {
+ PS_CONST,
+ PS_TEX,
+ PS_HANG,
+ PS_HANG_SLOW
+};
+
+enum vs_type {
+ VS_RECTPOSTEXFAST,
+};
+
+struct reg_info {
+ uint32_t reg_offset; ///< Memory mapped register offset
+ uint32_t reg_value; ///< register value
+};
+
+#include "shader_code_hang.h"
+#include "shader_code_gfx9.h"
+#include "shader_code_gfx10.h"
+#include "shader_code_gfx11.h"
+
+struct shader_test_cs_shader {
+ const uint32_t *shader;
+ uint32_t shader_size;
+ const struct reg_info *sh_reg;
+ uint32_t num_sh_reg;
+ const struct reg_info *context_reg;
+ uint32_t num_context_reg;
+};
+
+struct shader_test_ps_shader {
+ const uint32_t *shader;
+ unsigned shader_size;
+ const uint32_t patchinfo_code_size;
+ const uint32_t *patchinfo_code;
+ const uint32_t *patchinfo_code_offset;
+ const struct reg_info *sh_reg;
+ const uint32_t num_sh_reg;
+ const struct reg_info *context_reg;
+ const uint32_t num_context_reg;
+};
+
+struct shader_test_vs_shader {
+ const uint32_t *shader;
+ uint32_t shader_size;
+ const struct reg_info *sh_reg;
+ uint32_t num_sh_reg;
+ const struct reg_info *context_reg;
+ uint32_t num_context_reg;
+};
+
+static const struct shader_test_cs_shader shader_test_cs[AMDGPU_TEST_GFX_MAX][2] = {
+ // gfx9, cs_bufferclear
+ {{bufferclear_cs_shader_gfx9, sizeof(bufferclear_cs_shader_gfx9), bufferclear_cs_shader_registers_gfx9, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx9)},
+ // gfx9, cs_buffercopy
+ {buffercopy_cs_shader_gfx9, sizeof(buffercopy_cs_shader_gfx9), bufferclear_cs_shader_registers_gfx9, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx9)}},
+ // gfx10, cs_bufferclear
+ {{bufferclear_cs_shader_gfx10, sizeof(bufferclear_cs_shader_gfx10), bufferclear_cs_shader_registers_gfx9, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx9)},
+ // gfx10, cs_buffercopy
+ {buffercopy_cs_shader_gfx10, sizeof(bufferclear_cs_shader_gfx10), bufferclear_cs_shader_registers_gfx9, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx9)}},
+ // gfx11, cs_bufferclear
+ {{bufferclear_cs_shader_gfx11, sizeof(bufferclear_cs_shader_gfx11), bufferclear_cs_shader_registers_gfx11, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx11)},
+ // gfx11, cs_buffercopy
+ {buffercopy_cs_shader_gfx11, sizeof(bufferclear_cs_shader_gfx11), bufferclear_cs_shader_registers_gfx11, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx11)}},
+};
+
+#define SHADER_PS_INFO(_ps, _n) \
+ {ps_##_ps##_shader_gfx##_n, sizeof(ps_##_ps##_shader_gfx##_n), \
+ ps_##_ps##_shader_patchinfo_code_size_gfx##_n, \
+ ps_##_ps##_shader_patchinfo_code_gfx##_n, \
+ ps_##_ps##_shader_patchinfo_offset_gfx##_n, \
+ ps_##_ps##_sh_registers_gfx##_n, ps_##_ps##_num_sh_registers_gfx##_n, \
+ ps_##_ps##_context_registers_gfx##_n, ps_##_ps##_num_context_registers_gfx##_n}
+static const struct shader_test_ps_shader shader_test_ps[AMDGPU_TEST_GFX_MAX][2] = {
+ {SHADER_PS_INFO(const, 9), SHADER_PS_INFO(tex, 9)},
+ {SHADER_PS_INFO(const, 10), SHADER_PS_INFO(tex, 10)},
+ {SHADER_PS_INFO(const, 11), SHADER_PS_INFO(tex, 11)},
+};
+
+#define SHADER_VS_INFO(_vs, _n) \
+ {vs_##_vs##_shader_gfx##_n, sizeof(vs_##_vs##_shader_gfx##_n), \
+ vs_##_vs##_sh_registers_gfx##_n, vs_##_vs##_num_sh_registers_gfx##_n, \
+ vs_##_vs##_context_registers_gfx##_n, vs_##_vs##_num_context_registers_gfx##_n}
+static const struct shader_test_vs_shader shader_test_vs[AMDGPU_TEST_GFX_MAX][1] = {
+ {SHADER_VS_INFO(RectPosTexFast, 9)},
+ {SHADER_VS_INFO(RectPosTexFast, 10)},
+ {SHADER_VS_INFO(RectPosTexFast, 11)},
+};
+
+struct shader_test_gfx_info {
+ const uint32_t *preamble_cache;
+ uint32_t size_preamble_cache;
+ const uint32_t *cached_cmd;
+ uint32_t size_cached_cmd;
+ uint32_t sh_reg_base;
+ uint32_t context_reg_base;
+};
+
+#define SHADER_TEST_GFX_INFO(_n) \
+ preamblecache_gfx##_n, sizeof(preamblecache_gfx##_n), \
+ cached_cmd_gfx##_n, sizeof(cached_cmd_gfx##_n), \
+ sh_reg_base_gfx##_n, context_reg_base_gfx##_n
+
+static struct shader_test_gfx_info shader_test_gfx_info[AMDGPU_TEST_GFX_MAX] = {
+ {SHADER_TEST_GFX_INFO(9),},
+ {SHADER_TEST_GFX_INFO(10),},
+ {SHADER_TEST_GFX_INFO(11),},
+};
+#endif
|
|
[-]
[+]
|
Added |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/amdgpu/shader_code_gfx10.h
^
|
| @@ -0,0 +1,202 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+*/
+
+#ifndef _shader_code_gfx10_h_
+#define _shader_code_gfx10_h_
+
+static const uint32_t bufferclear_cs_shader_gfx10[] = {
+ 0xD7460004, 0x04010C08, 0x7E000204, 0x7E020205,
+ 0x7E040206, 0x7E060207, 0xE01C2000, 0x80000004,
+ 0xBF810000
+};
+
+static const uint32_t buffercopy_cs_shader_gfx10[] = {
+ 0xD7460001, 0x04010C08, 0xE00C2000, 0x80000201,
+ 0xBF8C3F70, 0xE01C2000, 0x80010201, 0xBF810000
+};
+
+static const uint32_t ps_const_shader_gfx10[] = {
+ 0x7E000200, 0x7E020201, 0x7E040202, 0x7E060203,
+ 0x5E000300, 0x5E020702, 0xBF800000, 0xBF800000,
+ 0xF8001C0F, 0x00000100, 0xBF810000
+};
+
+static const uint32_t ps_const_shader_patchinfo_code_size_gfx10 = 6;
+
+static const uint32_t ps_const_shader_patchinfo_code_gfx10[][10][6] = {
+ {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001890, 0x00000000 },
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001801, 0x00000000 },
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001803, 0x00000100 },
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001803, 0x00000300 },
+ { 0x5E000300, 0x5E020702, 0xBF800000, 0xBF800000, 0xF8001C0F, 0x00000100 },
+ { 0xD7690000, 0x00020300, 0xD7690001, 0x00020702, 0xF8001C0F, 0x00000100 },
+ { 0xD7680000, 0x00020300, 0xD7680001, 0x00020702, 0xF8001C0F, 0x00000100 },
+ { 0xD76A0000, 0x00020300, 0xD76A0001, 0x00020702, 0xF8001C0F, 0x00000100 },
+ { 0xD76B0000, 0x00020300, 0xD76B0001, 0x00020702, 0xF8001C0F, 0x00000100 },
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF800180F, 0x03020100 }
+ }
+};
+
+static const uint32_t ps_const_shader_patchinfo_offset_gfx10[] = {
+ 0x00000004
+};
+
+static const uint32_t ps_const_num_sh_registers_gfx10 = 2;
+
+static const struct reg_info ps_const_sh_registers_gfx10[] = {
+ {0x2C0A, 0x000C0000},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0000 },
+ {0x2C0B, 0x00000008}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000008 }
+};
+
+static const struct reg_info ps_const_context_registers_gfx10[] =
+{
+ {0xA1B4, 0x00000002}, //{ mmSPI_PS_INPUT_ADDR, 0x00000002 },
+ {0xA1B6, 0x00000000}, //{ mmSPI_PS_IN_CONTROL, 0x00000000 },
+ {0xA08F, 0x0000000F}, //{ mmCB_SHADER_MASK, 0x0000000F },
+ {0xA203, 0x00000010}, //{ mmDB_SHADER_CONTROL, 0x00000010 },
+ {0xA1C4, 0x00000000}, //{ mmSPI_SHADER_Z_FORMAT, 0x00000000 },
+ {0xA1B8, 0x00000000}, //{ mmSPI_BARYC_CNTL, 0x00000000 /* Always 0 for now */},
+ {0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 /* SI_EXPORT_FMT_FP16_ABGR */ }
+};
+
+static const uint32_t ps_const_num_context_registers_gfx10 = 7;
+
+static const uint32_t ps_tex_shader_gfx10[] = {
+ 0xBEFC030C, 0xBE8E047E, 0xBEFE0A7E, 0xC8080000,
+ 0xC80C0100, 0xC8090001, 0xC80D0101, 0xF0800F0A,
+ 0x00400402, 0x00000003, 0xBEFE040E, 0xBF8C0F70,
+ 0x5E000B04, 0x5E020F06, 0xBF800000, 0xBF800000,
+ 0xF8001C0F, 0x00000100, 0xBF810000
+};
+
+static const uint32_t ps_tex_shader_patchinfo_offset_gfx10[] = {
+ 0x0000000C
+};
+
+static const uint32_t ps_tex_shader_patchinfo_code_size_gfx10 = 6;
+
+static const uint32_t ps_tex_shader_patchinfo_code_gfx10[][10][6] = {
+ {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001890, 0x00000000 },
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001801, 0x00000004 },
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001803, 0x00000504 },
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001803, 0x00000704 },
+ { 0x5E000B04, 0x5E020F06, 0xBF800000, 0xBF800000, 0xF8001C0F, 0x00000100 },
+ { 0xD7690000, 0x00020B04, 0xD7690001, 0x00020F06, 0xF8001C0F, 0x00000100 },
+ { 0xD7680000, 0x00020B04, 0xD7680001, 0x00020F06, 0xF8001C0F, 0x00000100 },
+ { 0xD76A0000, 0x00020B04, 0xD76A0001, 0x00020F06, 0xF8001C0F, 0x00000100 },
+ { 0xD76B0000, 0x00020B04, 0xD76B0001, 0x00020F06, 0xF8001C0F, 0x00000100 },
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF800180F, 0x07060504 }
+ }
+};
+
+static const struct reg_info ps_tex_sh_registers_gfx10[] =
+{
+ {0x2C0A, 0xc0081}, //0x020C0080 }, //{ mmSPI_SHADER_PGM_RSRC1_PS, 0x020C0080 },
+ {0x2C0B, 0x00000018 }, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000018 }
+};
+
+static const uint32_t ps_tex_num_sh_registers_gfx10 = 2;
+
+// Holds Context Register Information
+static const struct reg_info ps_tex_context_registers_gfx10[] =
+{
+ {0xA1B4, 0x00000002}, //{ mmSPI_PS_INPUT_ADDR, 0x00000002 },
+ {0xA1B6, 0x00000001}, //{ mmSPI_PS_IN_CONTROL, 0x00000001 },
+ {0xA08F, 0x0000000F}, //{ mmCB_SHADER_MASK, 0x0000000F },
+ {0xA203, 0x00000010}, //{ mmDB_SHADER_CONTROL, 0x00000010 },
+ {0xA1C4, 0x00000000}, //{ mmSPI_SHADER_Z_FORMAT, 0x00000000 },
+ {0xA1B8, 0x00000000}, //{ mmSPI_BARYC_CNTL, 0x00000000 /* Always 0 for now */},
+ {0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 /* SI_EXPORT_FMT_FP16_ABGR */ }
+};
+
+static const uint32_t ps_tex_num_context_registers_gfx10 = 7;
+
+static const uint32_t vs_RectPosTexFast_shader_gfx10[] = {
+ 0x7E000B00, 0x060000F3, 0x7E020202, 0x7E040206,
+ 0x7C040080, 0x060000F3, 0xD5010001, 0x01AA0200,
+ 0x7E060203, 0xD5010002, 0x01AA0404, 0x7E080207,
+ 0x7C040080, 0xD5010000, 0x01A80101, 0xD5010001,
+ 0x01AA0601, 0x7E060208, 0x7E0A02F2, 0xD5010002,
+ 0x01A80902, 0xD5010004, 0x01AA0805, 0x7E0C0209,
+ 0xF80008CF, 0x05030100, 0xF800020F, 0x05060402,
+ 0xBF810000
+};
+
+static const struct reg_info vs_RectPosTexFast_sh_registers_gfx10[] =
+{
+ {0x2C4A, 0x080C0041 }, //{ mmSPI_SHADER_PGM_RSRC1_VS, 0x080C0041 },
+ {0x2C4B, 0x00000018 }, //{ mmSPI_SHADER_PGM_RSRC2_VS, 0x00000018 }
+};
+
+static const uint32_t vs_RectPosTexFast_num_sh_registers_gfx10 = 2;
+
+// Holds Context Register Information
+static const struct reg_info vs_RectPosTexFast_context_registers_gfx10[] =
+{
+ {0xA1B1, 0x00000000}, //{ mmSPI_VS_OUT_CONFIG, 0x00000000 },
+ {0xA1C3, 0x00000000}, //{ mmSPI_SHADER_POS_FORMAT, 0x00000000 /* Always 0 for now */}
+};
+
+static const uint32_t vs_RectPosTexFast_num_context_registers_gfx10 = 2;
+
+static const uint32_t preamblecache_gfx10[] = {
+ 0xc0026900, 0x81, 0x80000000, 0x40004000, 0xc0026900, 0x8c, 0xaa99aaaa, 0x0,
+ 0xc0026900, 0x90, 0x80000000, 0x40004000, 0xc0026900, 0x94, 0x80000000, 0x40004000,
+ 0xc0026900, 0xb4, 0x0, 0x3f800000, 0xc0016900, 0x103, 0x0,
+ 0xc0016900, 0x208, 0x0, 0xc0016900, 0x290, 0x0,
+ 0xc0016900, 0x2a1, 0x0, 0xc0026900, 0x2ad, 0x0, 0x0,
+ 0xc0016900, 0x2d5, 0x10000, 0xc0016900, 0x2dc, 0x0,
+ 0xc0066900, 0x2de, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc0026900, 0x2e5, 0x0, 0x0,
+ 0xc0056900, 0x2f9, 0x5, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
+ 0xc0046900, 0x310, 0, 0x3, 0, 0x100000, 0xc0026900, 0x316, 0xe, 0x20,
+ 0xc0016900, 0x349, 0x0, 0xc0016900, 0x358, 0x0, 0xc0016900, 0x367, 0x0,
+ 0xc0016900, 0x376, 0x0, 0xc0016900, 0x385, 0x0, 0xc0016900, 0x6, 0x0,
+ 0xc0056900, 0xe8, 0x0, 0x0, 0x0, 0x0, 0x0,
+ 0xc0076900, 0x1e1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+ 0xc0026900, 0x204, 0x90000, 0x4, 0xc0046900, 0x20c, 0x0, 0x0, 0x0, 0x0,
+ 0xc0016900, 0x2b2, 0x0, 0xc0026900, 0x30e, 0xffffffff, 0xffffffff,
+ 0xc0016900, 0x314, 0x0, 0xc0016900, 0x10a, 0, 0xc0016900, 0x2a6, 0, 0xc0016900, 0x210, 0,
+ 0xc0016900, 0x2db, 0, 0xc0016900, 0x1d4, 0, 0xc0002f00, 0x1, 0xc0016900, 0x1, 0x1, 0xc0016900, 0xe, 0x2,
+ 0xc0016900, 0x206, 0x300, 0xc0016900, 0x212, 0x200, 0xc0017900, 0x7b, 0x20, 0xc0017a00, 0x20000243, 0x0,
+ 0xc0017900, 0x249, 0, 0xc0017900, 0x24a, 0, 0xc0017900, 0x24b, 0, 0xc0017900, 0x259, 0xffffffff,
+ 0xc0017900, 0x25f, 0, 0xc0017900, 0x260, 0, 0xc0017900, 0x262, 0,
+ 0xc0017600, 0x45, 0x0, 0xc0017600, 0x6, 0x0,
+ 0xc0067600, 0x70, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+ 0xc0067600, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
+};
+
+static const uint32_t cached_cmd_gfx10[] = {
+ 0xc0016900, 0x0, 0x0, 0xc0026900, 0x3, 0x2a, 0x0,
+ 0xc0046900, 0xa, 0x0, 0x0, 0x0, 0x200020,
+ 0xc0016900, 0x83, 0xffff, 0xc0026900, 0x8e, 0xf, 0xf,
+ 0xc0056900, 0x105, 0x0, 0x0, 0x0, 0x0, 0x18,
+ 0xc0026900, 0x10b, 0x0, 0x0, 0xc0016900, 0x1e0, 0x0,
+ 0xc0036900, 0x200, 0x0, 0x10000, 0xcc0011,
+ 0xc0026900, 0x292, 0x20, 0x6020000,
+ 0xc0026900, 0x2b0, 0x0, 0x0, 0xc0016900, 0x2f8, 0x0
+};
+
+static const uint32_t sh_reg_base_gfx10 = 0x2C00;
|
|
[-]
[+]
|
Added |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/amdgpu/shader_code_gfx11.h
^
|
| @@ -0,0 +1,320 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+*/
+
+#ifndef _shader_code_gfx11_h_
+#define _shader_code_gfx11_h_
+
+static const uint32_t bufferclear_cs_shader_gfx11[] = {
+ 0xB0802006, 0xBF840003, 0x360000FF, 0x000003FF,
+ 0x7E020205, 0x7E040206, 0x7E060207, 0xBF870004,
+ 0xD6460004, 0x04010C08, 0x7E000204, 0xE01C0000,
+ 0x80800004, 0xBFB60003, 0xBFB00000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000
+};
+
+static const struct reg_info bufferclear_cs_shader_registers_gfx11[] = {
+ {0x2e12, 0x600C0041}, //{ mmCOMPUTE_PGM_RSRC1, 0x600C0041 },
+ {0x2e13, 0x00000090}, //{ mmCOMPUTE_PGM_RSRC2, 0x00000090 },
+ {0x2e07, 0x00000040}, //{ mmCOMPUTE_NUM_THREAD_X, 0x00000040 },
+ {0x2e08, 0x00000001}, //{ mmCOMPUTE_NUM_THREAD_Y, 0x00000001 },
+ {0x2e09, 0x00000001}, //{ mmCOMPUTE_NUM_THREAD_Z, 0x00000001 }
+};
+
+static const uint32_t buffercopy_cs_shader_gfx11[] = {
+ 0xB0802006, 0xBF840003, 0x360000FF, 0x000003FF,
+ 0xBF870001, 0xD6460001, 0x04010C08, 0xE00C0000,
+ 0x80800201, 0xBF8903F7, 0xE01C0000, 0x80810201,
+ 0xBFB60003, 0xBFB00000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000
+};
+
+static const uint32_t ps_const_shader_gfx11[] = {
+ 0xB0802006, 0xBF840003, 0x7E000200, 0x7E020201,
+ 0x7E040202, 0x7E060203, 0x5E000300, 0x5E020702,
+ 0xBF800000, 0xBF800000, 0xF8000803, 0x00000100,
+ 0xBFB00000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000
+};
+
+static const uint32_t ps_const_shader_patchinfo_code_size_gfx11 = 6;
+
+static const uint32_t ps_const_shader_patchinfo_code_gfx11[][10][6] = {
+ {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000890, 0x00000000 }, // SI_EXPORT_FMT_ZERO
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000801, 0x00000000 }, // SI_EXPORT_FMT_32_R
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_32_GR
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000803, 0x00000300 }, // SI_EXPORT_FMT_32_AR
+ { 0x5E000300, 0x5E020702, 0xBF800000, 0xBF800000, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_FP16_ABGR
+ { 0xD7220000, 0x00020300, 0xD7220001, 0x00020702, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_UNORM16_ABGR
+ { 0xD7210000, 0x00020300, 0xD7210001, 0x00020702, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_SNORM16_ABGR
+ { 0xD7230000, 0x00020300, 0xD7230001, 0x00020702, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_uint32_t16_ABGR
+ { 0xD7240000, 0x00020300, 0xD7240001, 0x00020702, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_SINT16_ABGR
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF800080F, 0x03020100 } // SI_EXPORT_FMT_32_ABGR
+ }
+};
+
+static const uint32_t ps_const_shader_patchinfo_offset_gfx11[] = {
+ 0x00000006
+};
+
+static const uint32_t ps_const_num_sh_registers_gfx11 = 2;
+
+static const struct reg_info ps_const_sh_registers_gfx11[] = {
+ {0x2C0A, 0x020C0000}, //{ mmSPI_SHADER_PGM_RSRC1_PS, 0x020C0000 },
+ {0x2C0B, 0x00000008}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000008 }
+};
+
+static const struct reg_info ps_const_context_registers_gfx11[] = {
+ {0xA1B4, 0x00000002 }, //{ mmSPI_PS_INPUT_ADDR, 0x00000002 },
+ {0xA1B6, 0x00000000 }, //{ mmSPI_PS_IN_CONTROL, 0x00000000 },
+ {0xA08F, 0x0000000F }, //{ mmCB_SHADER_MASK, 0x0000000F },
+ {0xA203, 0x00000010 }, //{ mmDB_SHADER_CONTROL, 0x00000010 },
+ {0xA1C4, 0x00000000 }, //{ mmSPI_SHADER_Z_FORMAT, 0x00000000 },
+ {0xA1B8, 0x00000000 }, //{ mmSPI_BARYC_CNTL, 0x00000000 /* Always 0 for now */},
+ {0xA1C5, 0x00000004 }, //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 /* SI_EXPORT_FMT_FP16_ABGR */ }
+};
+
+static const uint32_t ps_const_num_context_registers_gfx11 = 7;
+
+static const uint32_t ps_tex_shader_gfx11[] =
+{
+ 0xB0802006, 0xBF840003, 0xBEFD000C, 0xBE8E017E,
+ 0xBEFE1D7E, 0xCE000003, 0xCE000102, 0xCD000104,
+ 0x040E0103, 0xCD000000, 0x040A0102, 0xBF870112,
+ 0xCD010703, 0x04120303, 0xCD010700, 0x04020302,
+ 0x8BFE0E7E, 0xF06C0F05, 0x08000003, 0x00000000,
+ 0xBEFE010E, 0xBF8903F7, 0x5E000300, 0x5E020702,
+ 0xBF800000, 0xBF800000, 0xF8000803, 0x00000100,
+ 0xBFB00000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+ 0xBF9F0000
+};
+
+static const uint32_t ps_tex_shader_patchinfo_offset_gfx11[] =
+{
+ 0x00000016
+};
+
+// Denotes the Patch Info Code Length
+static const uint32_t ps_tex_shader_patchinfo_code_size_gfx11 = 6;
+
+static const uint32_t ps_tex_shader_patchinfo_code_gfx11[][10][6] =
+{
+ {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000890, 0x00000000 }, // SI_EXPORT_FMT_ZERO
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000801, 0x00000000 }, // SI_EXPORT_FMT_32_R
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_32_GR
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000803, 0x00000300 }, // SI_EXPORT_FMT_32_AR
+ { 0x5E000300, 0x5E020702, 0xBF800000, 0xBF800000, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_FP16_ABGR
+ { 0xD7220000, 0x00020300, 0xD7220001, 0x00020702, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_UNORM16_ABGR
+ { 0xD7210000, 0x00020300, 0xD7210001, 0x00020702, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_SNORM16_ABGR
+ { 0xD7230000, 0x00020300, 0xD7230001, 0x00020702, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_uint32_t16_ABGR
+ { 0xD7240000, 0x00020300, 0xD7240001, 0x00020702, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_SINT16_ABGR
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF800080F, 0x03020100 } // SI_EXPORT_FMT_32_ABGR
+ }
+};
+// Holds Sh Register Information
+static const struct reg_info ps_tex_sh_registers_gfx11[] =
+{
+ {0x2C0A, 0x020C0081 }, //{ mmSPI_SHADER_PGM_RSRC1_PS, 0x020C0081 },
+ {0x2C0B, 0x00000018 } //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000018 }
+};
+
|
|
[-]
[+]
|
Added |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/amdgpu/shader_code_gfx9.h
^
|
| @@ -0,0 +1,204 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+*/
+
+#ifndef _shader_code_gfx9_h_
+#define _shader_code_gfx9_h_
+
+static const uint32_t bufferclear_cs_shader_gfx9[] = {
+ 0x260000ff, 0x000003ff, 0xd1fd0000, 0x04010c08,
+ 0x7e020280, 0x7e040204, 0x7e060205, 0x7e080206,
+ 0x7e0a0207, 0xe01c2000, 0x80000200, 0xbf8c0000,
+ 0xbf810000
+};
+
+static const struct reg_info bufferclear_cs_shader_registers_gfx9[] = {
+ {0x2e12, 0x000C0041}, //{ mmCOMPUTE_PGM_RSRC1, 0x000C0041 },
+ {0x2e13, 0x00000090}, //{ mmCOMPUTE_PGM_RSRC2, 0x00000090 },
+ {0x2e07, 0x00000040}, //{ mmCOMPUTE_NUM_THREAD_X, 0x00000040 },
+ {0x2e08, 0x00000001}, //{ mmCOMPUTE_NUM_THREAD_Y, 0x00000001 },
+ {0x2e09, 0x00000001}, //{ mmCOMPUTE_NUM_THREAD_Z, 0x00000001 }
+};
+
+static const uint32_t buffercopy_cs_shader_gfx9[] = {
+ 0x260000ff, 0x000003ff, 0xd1fd0000, 0x04010c08,
+ 0x7e020280, 0xe00c2000, 0x80000200, 0xbf8c0f70,
+ 0xe01c2000, 0x80010200, 0xbf810000
+};
+
+static const uint32_t ps_const_shader_gfx9[] = {
+ 0x7E000200, 0x7E020201, 0x7E040202, 0x7E060203,
+ 0xD2960000, 0x00020300, 0xD2960001, 0x00020702,
+ 0xC4001C0F, 0x00000100, 0xBF810000
+};
+
+static const uint32_t ps_const_shader_patchinfo_code_size_gfx9 = 6;
+
+static const uint32_t ps_const_shader_patchinfo_code_gfx9[][10][6] = {
+ {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001890, 0x00000000 },
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001801, 0x00000000 },
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001803, 0x00000100 },
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001803, 0x00000300 },
+ { 0xD2960000, 0x00020300, 0xD2960001, 0x00020702, 0xC4001C0F, 0x00000100 },
+ { 0xD2950000, 0x00020300, 0xD2950001, 0x00020702, 0xC4001C0F, 0x00000100 },
+ { 0xD2940000, 0x00020300, 0xD2940001, 0x00020702, 0xC4001C0F, 0x00000100 },
+ { 0xD2970000, 0x00020300, 0xD2970001, 0x00020702, 0xC4001C0F, 0x00000100 },
+ { 0xD2980000, 0x00020300, 0xD2980001, 0x00020702, 0xC4001C0F, 0x00000100 },
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC400180F, 0x03020100 }
+ }
+};
+
+static const uint32_t ps_const_shader_patchinfo_offset_gfx9[] = {
+ 0x00000004
+};
+
+static const uint32_t ps_const_num_sh_registers_gfx9 = 2;
+
+static const struct reg_info ps_const_sh_registers_gfx9[] = {
+ {0x2C0A, 0x000C0040},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0040 },
+ {0x2C0B, 0x00000008}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000008 }
+};
+
+static const uint32_t ps_const_num_context_registers_gfx9 = 7;
+
+static const struct reg_info ps_const_context_registers_gfx9[] = {
+ {0xA1B4, 0x00000002}, //{ mmSPI_PS_INPUT_ADDR, 0x00000002 },
+ {0xA1B6, 0x00000000}, //{ mmSPI_PS_IN_CONTROL, 0x00000000 },
+ {0xA08F, 0x0000000F}, //{ mmCB_SHADER_MASK, 0x0000000F },
+ {0xA203, 0x00000010}, //{ mmDB_SHADER_CONTROL, 0x00000010 },
+ {0xA1C4, 0x00000000}, //{ mmSPI_SHADER_Z_FORMAT, 0x00000000 },
+ {0xA1B8, 0x00000000}, //{ mmSPI_BARYC_CNTL, 0x00000000 /* Always 0 for now */},
+ {0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 }
+};
+
+static const uint32_t ps_tex_shader_gfx9[] = {
+ 0xBEFC000C, 0xBE8E017E, 0xBEFE077E, 0xD4180000,
+ 0xD4190001, 0xD41C0100, 0xD41D0101, 0xF0800F00,
+ 0x00400206, 0xBEFE010E, 0xBF8C0F70, 0xD2960000,
+ 0x00020702, 0xD2960001, 0x00020B04, 0xC4001C0F,
+ 0x00000100, 0xBF810000
+};
+
+static const uint32_t ps_tex_shader_patchinfo_offset_gfx9[] = {
+ 0x0000000B
+};
+
+static const uint32_t ps_tex_shader_patchinfo_code_size_gfx9 = 6;
+
+static const uint32_t ps_tex_shader_patchinfo_code_gfx9[][10][6] = {
+ {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001890, 0x00000000 },
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001801, 0x00000002 },
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001803, 0x00000302 },
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001803, 0x00000502 },
+ { 0xD2960000, 0x00020702, 0xD2960001, 0x00020B04, 0xC4001C0F, 0x00000100 },
+ { 0xD2950000, 0x00020702, 0xD2950001, 0x00020B04, 0xC4001C0F, 0x00000100 },
+ { 0xD2940000, 0x00020702, 0xD2940001, 0x00020B04, 0xC4001C0F, 0x00000100 },
+ { 0xD2970000, 0x00020702, 0xD2970001, 0x00020B04, 0xC4001C0F, 0x00000100 },
+ { 0xD2980000, 0x00020702, 0xD2980001, 0x00020B04, 0xC4001C0F, 0x00000100 },
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC400180F, 0x05040302 }
+ }
+};
+
+static const uint32_t ps_tex_num_sh_registers_gfx9 = 2;
+static const struct reg_info ps_tex_sh_registers_gfx9[] = {
+ {0x2C0A, 0x000C0081},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0081 },
+ {0x2C0B, 0x00000018}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000018 }
+};
+
+static const uint32_t ps_tex_num_context_registers_gfx9 = 7;
+
+static const struct reg_info ps_tex_context_registers_gfx9[] = {
+ {0xA1B4, 0x00000002}, //{ mmSPI_PS_INPUT_ADDR, 0x00000002 },
+ {0xA1B6, 0x00000001}, //{ mmSPI_PS_IN_CONTROL, 0x00000001 },
+ {0xA08F, 0x0000000F}, //{ mmCB_SHADER_MASK, 0x0000000F },
+ {0xA203, 0x00000010}, //{ mmDB_SHADER_CONTROL, 0x00000010 },
+ {0xA1C4, 0x00000000}, //{ mmSPI_SHADER_Z_FORMAT, 0x00000000 },
+ {0xA1B8, 0x00000000}, //{ mmSPI_BARYC_CNTL, 0x00000000 /* Always 0 for now */},
+ {0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 }
+};
+
+static const uint32_t vs_RectPosTexFast_shader_gfx9[] = {
+ 0x7E000B00, 0x020000F3, 0xD042000A, 0x00010100,
+ 0x7E020202, 0x7E040200, 0x020000F3, 0x7E060206,
+ 0x7E080204, 0xD1000001, 0x002A0302, 0x7C840080,
+ 0x7E000200, 0x7E040203, 0x7E0A0201, 0xD1000003,
+ 0x002A0704, 0x7E0C0207, 0x7E0E0205, 0x00000101,
+ 0x00020505, 0x7E040208, 0x7E0A02F2, 0x00060903,
+ 0x00080D07, 0x7E0C0209, 0xC40008CF, 0x05020100,
+ 0xC400020F, 0x05060403, 0xBF810000
+};
+
+static const struct reg_info vs_RectPosTexFast_sh_registers_gfx9[] =
+{
+ {0x2C4A, 0x000C0081}, //{ mmSPI_SHADER_PGM_RSRC1_VS, 0x000C0081 },
+ {0x2C4B, 0x00000018}, //{ mmSPI_SHADER_PGM_RSRC2_VS, 0x00000018 }
+};
+
+static const uint32_t vs_RectPosTexFast_num_sh_registers_gfx9 = 2;
+
+// Holds Context Register Information
+static const struct reg_info vs_RectPosTexFast_context_registers_gfx9[] =
+{
+ {0xA1B1, 0x00000000}, //{ mmSPI_VS_OUT_CONFIG, 0x00000000 },
+ {0xA1C3, 0x00000000}, //{ mmSPI_SHADER_POS_FORMAT, 0x00000000 /* Always 0 for now */}
+};
+
+static const uint32_t vs_RectPosTexFast_num_context_registers_gfx9 = 2;
+
+static const uint32_t preamblecache_gfx9[] = {
+ 0xc0026900, 0x81, 0x80000000, 0x40004000, 0xc0026900, 0x8c, 0xaa99aaaa, 0x0,
+ 0xc0026900, 0x90, 0x80000000, 0x40004000, 0xc0026900, 0x94, 0x80000000, 0x40004000,
+ 0xc0026900, 0xb4, 0x0, 0x3f800000, 0xc0016900, 0x103, 0x0,
+ 0xc0016900, 0x208, 0x0, 0xc0016900, 0x290, 0x0,
+ 0xc0016900, 0x2a1, 0x0, 0xc0026900, 0x2ad, 0x0, 0x0,
+ 0xc0016900, 0x2d5, 0x10000, 0xc0016900, 0x2dc, 0x0,
+ 0xc0066900, 0x2de, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc0026900, 0x2e5, 0x0, 0x0,
+ 0xc0056900, 0x2f9, 0x5, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
+ 0xc0036900, 0x311, 0x3, 0, 0x100000, 0xc0026900, 0x316, 0x1e, 0x20,
+ 0xc0016900, 0x349, 0x0, 0xc0016900, 0x358, 0x0, 0xc0016900, 0x367, 0x0,
+ 0xc0016900, 0x376, 0x0, 0xc0016900, 0x385, 0x0, 0xc0016900, 0x19, 0x0,
+ 0xc0056900, 0xe8, 0x0, 0x0, 0x0, 0x0, 0x0,
+ 0xc0076900, 0x1e1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+ 0xc0026900, 0x204, 0x90000, 0x4, 0xc0046900, 0x20c, 0x0, 0x0, 0x0, 0x0,
+ 0xc0016900, 0x2b2, 0x0, 0xc0026900, 0x30e, 0xffffffff, 0xffffffff,
+ 0xc0016900, 0x314, 0x0, 0xc0016900, 0x2a6, 0, 0xc0016900, 0x210, 0,
+ 0xc0002f00, 0x1, 0xc0016900, 0x1, 0x1,
+ 0xc0016900, 0x18, 0x2, 0xc0016900, 0x206, 0x300, 0xc0017900, 0x20000243, 0x0,
+ 0xc0017900, 0x248, 0xffffffff, 0xc0017900, 0x249, 0x0, 0xc0017900, 0x24a, 0x0,
+ 0xc0017900, 0x24b, 0x0
+};
+
+static const uint32_t cached_cmd_gfx9[] = {
+ 0xc0016900, 0x0, 0x0, 0xc0026900, 0x3, 0x2a, 0x0,
+ 0xc0046900, 0xa, 0x0, 0x0, 0x0, 0x200020,
+ 0xc0016900, 0x83, 0xffff, 0xc0026900, 0x8e, 0xf, 0xf,
+ 0xc0056900, 0x105, 0x0, 0x0, 0x0, 0x0, 0x12,
+ 0xc0026900, 0x10b, 0x0, 0x0, 0xc0016900, 0x1e0, 0x0,
+ 0xc0036900, 0x200, 0x0, 0x10000, 0xcc0011,
+ 0xc0026900, 0x292, 0x20, 0x60201b8,
+ 0xc0026900, 0x2b0, 0x0, 0x0, 0xc0016900, 0x2f8, 0x0
+};
|
|
[-]
[+]
|
Added |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/amdgpu/shader_code_hang.h
^
|
| @@ -0,0 +1,104 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+*/
+
+#ifndef _shader_code_hang_h_
+#define _shader_code_hang_h_
+
+static const unsigned int memcpy_shader_hang[] = {
+ 0xFFFFFFFF, 0xBEFE0A7E, 0xBEFC0304, 0xC0C20100,
+ 0xC0800300, 0xC8080000, 0xC80C0100, 0xC8090001,
+ 0xC80D0101, 0xBF8C007F, 0xF0800F00, 0x00010002,
+ 0xBEFE040C, 0xBF8C0F70, 0xBF800000, 0xBF800000,
+ 0xF800180F, 0x03020100, 0xBF810000
+};
+
+struct shader_test_shader_bin {
+ const uint32_t *shader;
+ uint32_t header_length;
+ uint32_t body_length;
+ uint32_t foot_length;
+};
+
+static const unsigned int memcpy_cs_hang_slow_ai_codes[] = {
+ 0xd1fd0000, 0x04010c08, 0xe00c2000, 0x80000100,
+ 0xbf8c0f70, 0xe01c2000, 0x80010100, 0xbf810000
+};
+
+static struct shader_test_shader_bin memcpy_cs_hang_slow_ai = {
+ memcpy_cs_hang_slow_ai_codes, 4, 3, 1
+};
+
+static const unsigned int memcpy_cs_hang_slow_rv_codes[] = {
+ 0x8e00860c, 0x32000000, 0xe00c2000, 0x80010100,
+ 0xbf8c0f70, 0xe01c2000, 0x80020100, 0xbf810000
+};
+
+static struct shader_test_shader_bin memcpy_cs_hang_slow_rv = {
+ memcpy_cs_hang_slow_rv_codes, 4, 3, 1
+};
+
+static const unsigned int memcpy_cs_hang_slow_nv_codes[] = {
+ 0xd7460000, 0x04010c08, 0xe00c2000, 0x80000100,
+ 0xbf8c0f70, 0xe01ca000, 0x80010100, 0xbf810000
+};
+
+static struct shader_test_shader_bin memcpy_cs_hang_slow_nv = {
+ memcpy_cs_hang_slow_nv_codes, 4, 3, 1
+};
+
+
+static const unsigned int memcpy_ps_hang_slow_ai_codes[] = {
+ 0xbefc000c, 0xbe8e017e, 0xbefe077e, 0xd4080000,
+ 0xd4090001, 0xd40c0100, 0xd40d0101, 0xf0800f00,
+ 0x00400002, 0xbefe010e, 0xbf8c0f70, 0xbf800000,
+ 0xbf800000, 0xbf800000, 0xbf800000, 0xc400180f,
+ 0x03020100, 0xbf810000
+};
+
+static struct shader_test_shader_bin memcpy_ps_hang_slow_ai = {
+ memcpy_ps_hang_slow_ai_codes, 7, 2, 9
+};
+
+static const unsigned int memcpy_ps_hang_slow_navi10_codes[] = {
+ 0xBEFC030C,0xBE8E047E,0xBEFE0A7E,0xC8080000,
+ 0xC80C0100,0xC8090001,0xC80D0101,0xF0800F0A,
+ 0x00400402,0x00000003,0xBEFE040E,0xBF8C0F70,
+ 0xBF800000,0xBF800000,0xBF800000,0xBF800000,
+ 0xF800180F,0x07060504,0xBF810000
+};
+
+static struct shader_test_shader_bin memcpy_ps_hang_slow_navi10 = {
+ memcpy_ps_hang_slow_navi10_codes, 7, 3, 9
+};
+
+static const unsigned int memcpy_ps_hang_slow_navi21_codes[] = {
+ 0xBEFC030C, 0xBE8E047E, 0xBEFE0A7E, 0xC8080000, 0xC8000100, 0xC8090001, 0xC8010101, 0x87FE0E7E, // header
+ 0xF0800F0A, 0x00400002, 0x00000000, // body - image_sample instruction
+ 0xBFA3FFE3, 0xBEFE040E, 0xBF8C3F70, 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF800180F, 0x03020100, 0xBF810000 // footer
+};
+
+static struct shader_test_shader_bin memcpy_ps_hang_slow_navi21 = {
+ memcpy_ps_hang_slow_navi21_codes, 8, 3, 10
+};
+
+#endif
|
|
[-]
[+]
|
Added |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/amdgpu/shader_test_util.c
^
|
| @@ -0,0 +1,2156 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <string.h>
+
+#include "CUnit/Basic.h"
+#include "amdgpu_test.h"
+#include "shader_code.h"
+
+#define PACKET3_DISPATCH_DIRECT 0x15
+#define PACKET3_CONTEXT_CONTROL 0x28
+#define PACKET3_DRAW_INDEX_AUTO 0x2D
+#define PACKET3_SET_CONTEXT_REG 0x69
+#define PACKET3_SET_SH_REG 0x76
+#define PACKET3_SET_SH_REG_OFFSET 0x77
+#define PACKET3_SET_UCONFIG_REG 0x79
+#define PACKET3_SET_SH_REG_INDEX 0x9B
+
+#define PACKET_TYPE3 3
+#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
+ (((op) & 0xFF) << 8) | \
+ ((n) & 0x3FFF) << 16)
+#define PACKET3_COMPUTE(op, n) PACKET3(op, n) | (1 << 1)
+
+
+struct shader_test_bo {
+ amdgpu_bo_handle bo;
+ unsigned size;
+ unsigned heap;
+ void *ptr;
+ uint64_t mc_address;
+ amdgpu_va_handle va;
+};
+
+struct shader_test_draw {
+ struct shader_test_bo ps_bo;
+ enum ps_type ps_type;
+ struct shader_test_bo vs_bo;
+ enum vs_type vs_type;
+};
+struct shader_test_dispatch {
+ struct shader_test_bo cs_bo;
+ enum cs_type cs_type;
+};
+
+struct shader_test_info {
+ amdgpu_device_handle device_handle;
+ enum amdgpu_test_gfx_version version;
+ unsigned ip;
+ unsigned ring;
+ int hang;
+ int hang_slow;
+};
+
+struct shader_test_priv {
+ const struct shader_test_info *info;
+ unsigned cmd_curr;
+
+ union {
+ struct shader_test_draw shader_draw;
+ struct shader_test_dispatch shader_dispatch;
+ };
+ struct shader_test_bo vtx_attributes_mem;
+ struct shader_test_bo cmd;
+ struct shader_test_bo src;
+ struct shader_test_bo dst;
+};
+
+static int shader_test_bo_alloc(amdgpu_device_handle device_handle,
+ struct shader_test_bo *shader_test_bo)
+{
+ return amdgpu_bo_alloc_and_map(device_handle, shader_test_bo->size, 4096,
+ shader_test_bo->heap, 0,
+ &(shader_test_bo->bo), (void **)&(shader_test_bo->ptr),
+ &(shader_test_bo->mc_address), &(shader_test_bo->va));
+}
+
+static int shader_test_bo_free(struct shader_test_bo *shader_test_bo)
+{
+ return amdgpu_bo_unmap_and_free(shader_test_bo->bo, shader_test_bo->va,
+ shader_test_bo->mc_address,
+ shader_test_bo->size);
+}
+
+void shader_test_for_each(amdgpu_device_handle device_handle, unsigned ip,
+ void (*fn)(struct shader_test_info *test_info))
+{
+ int r;
+ uint32_t ring_id;
+ struct shader_test_info test_info = {0};
+ struct drm_amdgpu_info_hw_ip info = {0};
+
+ r = amdgpu_query_hw_ip_info(device_handle, ip, 0, &info);
+ CU_ASSERT_EQUAL(r, 0);
+ if (!info.available_rings) {
+ printf("SKIP ... as there's no %s ring\n",
+ (ip == AMDGPU_HW_IP_GFX) ? "graphics": "compute");
+ return;
+ }
+
+ switch (info.hw_ip_version_major) {
+ case 9:
+ test_info.version = AMDGPU_TEST_GFX_V9;
+ break;
+ case 10:
+ test_info.version = AMDGPU_TEST_GFX_V10;
+ break;
+ case 11:
+ test_info.version = AMDGPU_TEST_GFX_V11;
+ break;
+ default:
+ printf("SKIP ... unsupported gfx version %d\n", info.hw_ip_version_major);
+ return;
+ }
+
+ test_info.device_handle = device_handle;
+ test_info.ip = ip;
+
+ printf("\n");
+ for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
+ printf("%s ring %d\n", (ip == AMDGPU_HW_IP_GFX) ? "graphics": "compute",
+ ring_id);
+ test_info.ring = ring_id;
+ fn(&test_info);
+ }
+}
+
+static void write_context_control(struct shader_test_priv *test_priv)
+{
+ int i = test_priv->cmd_curr;
+ uint32_t *ptr = test_priv->cmd.ptr;
+
+ if (test_priv->info->ip == AMDGPU_HW_IP_GFX) {
+ ptr[i++] = PACKET3(PACKET3_CONTEXT_CONTROL, 1);
+ ptr[i++] = 0x80000000;
+ ptr[i++] = 0x80000000;
+ }
+
+ test_priv->cmd_curr = i;
+}
+
+static void shader_test_load_shader_hang_slow(struct shader_test_bo *shader_bo,
+ struct shader_test_shader_bin *shader_bin)
+{
+ int i, j, loop;
+
+ loop = (shader_bo->size / sizeof(uint32_t) - shader_bin->header_length
+ - shader_bin->foot_length) / shader_bin->body_length;
+
+ memcpy(shader_bo->ptr, shader_bin->shader, shader_bin->header_length * sizeof(uint32_t));
+
+ j = shader_bin->header_length;
+ for (i = 0; i < loop; i++) {
+ memcpy(shader_bo->ptr + j,
+ shader_bin->shader + shader_bin->header_length,
+ shader_bin->body_length * sizeof(uint32_t));
+ j += shader_bin->body_length;
+ }
+
+ memcpy(shader_bo->ptr + j,
+ shader_bin->shader + shader_bin->header_length + shader_bin->body_length,
+ shader_bin->foot_length * sizeof(uint32_t));
+}
+
+static void amdgpu_dispatch_load_cs_shader_hang_slow(struct shader_test_priv *test_priv)
+{
+ struct amdgpu_gpu_info gpu_info = {0};
+ struct shader_test_shader_bin *cs_shader_bin;
+ int r;
+
+ r = amdgpu_query_gpu_info(test_priv->info->device_handle, &gpu_info);
+ CU_ASSERT_EQUAL(r, 0);
+
+ switch (gpu_info.family_id) {
+ case AMDGPU_FAMILY_AI:
+ cs_shader_bin = &memcpy_cs_hang_slow_ai;
+ break;
+ case AMDGPU_FAMILY_RV:
+ cs_shader_bin = &memcpy_cs_hang_slow_rv;
+ break;
+ default:
+ cs_shader_bin = &memcpy_cs_hang_slow_nv;
+ break;
+ }
+
+ shader_test_load_shader_hang_slow(&test_priv->shader_dispatch.cs_bo, cs_shader_bin);
+}
+
+static void amdgpu_dispatch_load_cs_shader(struct shader_test_priv *test_priv)
+{
+ if (test_priv->info->hang) {
+ if (test_priv->info->hang_slow)
+ amdgpu_dispatch_load_cs_shader_hang_slow(test_priv);
+ else
+ memcpy(test_priv->shader_dispatch.cs_bo.ptr, memcpy_shader_hang,
+ sizeof(memcpy_shader_hang));
+ } else {
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/amdgpu/vce_tests.c
^
|
| @@ -96,7 +96,7 @@
CU_BOOL suite_vce_tests_enable(void)
{
- uint32_t version, feature, asic_id;
+ uint32_t version, feature;
CU_BOOL ret_mv = CU_FALSE;
if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
@@ -107,7 +107,6 @@
chip_rev = device_handle->info.chip_rev;
chip_id = device_handle->info.chip_external_rev;
ids_flags = device_handle->info.ids_flags;
- asic_id = device_handle->info.asic_id;
amdgpu_query_firmware_version(device_handle, AMDGPU_INFO_FW_VCE, 0,
0, &version, &feature);
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/amdgpu/vcn_tests.c
^
|
| @@ -22,20 +22,65 @@
*/
#include <stdio.h>
+#include <string.h>
#include <inttypes.h>
+#include <unistd.h>
#include "CUnit/Basic.h"
+#include <unistd.h>
#include "util_math.h"
#include "amdgpu_test.h"
#include "amdgpu_drm.h"
#include "amdgpu_internal.h"
#include "decode_messages.h"
+#include "frame.h"
#define IB_SIZE 4096
#define MAX_RESOURCES 16
+#define DECODE_CMD_MSG_BUFFER 0x00000000
+#define DECODE_CMD_DPB_BUFFER 0x00000001
+#define DECODE_CMD_DECODING_TARGET_BUFFER 0x00000002
+#define DECODE_CMD_FEEDBACK_BUFFER 0x00000003
+#define DECODE_CMD_PROB_TBL_BUFFER 0x00000004
+#define DECODE_CMD_SESSION_CONTEXT_BUFFER 0x00000005
+#define DECODE_CMD_BITSTREAM_BUFFER 0x00000100
+#define DECODE_CMD_IT_SCALING_TABLE_BUFFER 0x00000204
+#define DECODE_CMD_CONTEXT_BUFFER 0x00000206
+
+#define DECODE_IB_PARAM_DECODE_BUFFER (0x00000001)
+
+#define DECODE_CMDBUF_FLAGS_MSG_BUFFER (0x00000001)
+#define DECODE_CMDBUF_FLAGS_DPB_BUFFER (0x00000002)
+#define DECODE_CMDBUF_FLAGS_BITSTREAM_BUFFER (0x00000004)
+#define DECODE_CMDBUF_FLAGS_DECODING_TARGET_BUFFER (0x00000008)
+#define DECODE_CMDBUF_FLAGS_FEEDBACK_BUFFER (0x00000010)
+#define DECODE_CMDBUF_FLAGS_IT_SCALING_BUFFER (0x00000200)
+#define DECODE_CMDBUF_FLAGS_CONTEXT_BUFFER (0x00000800)
+#define DECODE_CMDBUF_FLAGS_PROB_TBL_BUFFER (0x00001000)
+#define DECODE_CMDBUF_FLAGS_SESSION_CONTEXT_BUFFER (0x00100000)
+
+static bool vcn_dec_sw_ring = false;
+static bool vcn_unified_ring = false;
+
+#define H264_NAL_TYPE_NON_IDR_SLICE 1
+#define H264_NAL_TYPE_DP_A_SLICE 2
+#define H264_NAL_TYPE_DP_B_SLICE 3
+#define H264_NAL_TYPE_DP_C_SLICE 0x4
+#define H264_NAL_TYPE_IDR_SLICE 0x5
+#define H264_NAL_TYPE_SEI 0x6
+#define H264_NAL_TYPE_SEQ_PARAM 0x7
+#define H264_NAL_TYPE_PIC_PARAM 0x8
+#define H264_NAL_TYPE_ACCESS_UNIT 0x9
+#define H264_NAL_TYPE_END_OF_SEQ 0xa
+#define H264_NAL_TYPE_END_OF_STREAM 0xb
+#define H264_NAL_TYPE_FILLER_DATA 0xc
+#define H264_NAL_TYPE_SEQ_EXTENSION 0xd
+
+#define H264_START_CODE 0x000001
+
struct amdgpu_vcn_bo {
amdgpu_bo_handle handle;
amdgpu_va_handle va_handle;
@@ -44,6 +89,48 @@
uint8_t *ptr;
};
+typedef struct rvcn_decode_buffer_s {
+ unsigned int valid_buf_flag;
+ unsigned int msg_buffer_address_hi;
+ unsigned int msg_buffer_address_lo;
+ unsigned int dpb_buffer_address_hi;
+ unsigned int dpb_buffer_address_lo;
+ unsigned int target_buffer_address_hi;
+ unsigned int target_buffer_address_lo;
+ unsigned int session_contex_buffer_address_hi;
+ unsigned int session_contex_buffer_address_lo;
+ unsigned int bitstream_buffer_address_hi;
+ unsigned int bitstream_buffer_address_lo;
+ unsigned int context_buffer_address_hi;
+ unsigned int context_buffer_address_lo;
+ unsigned int feedback_buffer_address_hi;
+ unsigned int feedback_buffer_address_lo;
+ unsigned int luma_hist_buffer_address_hi;
+ unsigned int luma_hist_buffer_address_lo;
+ unsigned int prob_tbl_buffer_address_hi;
+ unsigned int prob_tbl_buffer_address_lo;
+ unsigned int sclr_coeff_buffer_address_hi;
+ unsigned int sclr_coeff_buffer_address_lo;
+ unsigned int it_sclr_table_buffer_address_hi;
+ unsigned int it_sclr_table_buffer_address_lo;
+ unsigned int sclr_target_buffer_address_hi;
+ unsigned int sclr_target_buffer_address_lo;
+ unsigned int cenc_size_info_buffer_address_hi;
+ unsigned int cenc_size_info_buffer_address_lo;
+ unsigned int mpeg2_pic_param_buffer_address_hi;
+ unsigned int mpeg2_pic_param_buffer_address_lo;
+ unsigned int mpeg2_mb_control_buffer_address_hi;
+ unsigned int mpeg2_mb_control_buffer_address_lo;
+ unsigned int mpeg2_idct_coeff_buffer_address_hi;
+ unsigned int mpeg2_idct_coeff_buffer_address_lo;
+} rvcn_decode_buffer_t;
+
+typedef struct rvcn_decode_ib_package_s {
+ unsigned int package_size;
+ unsigned int package_type;
+} rvcn_decode_ib_package_t;
+
+
struct amdgpu_vcn_reg {
uint32_t data0;
uint32_t data1;
@@ -52,6 +139,23 @@
uint32_t cntl;
};
+typedef struct BufferInfo_t {
+ uint32_t numOfBitsInBuffer;
+ const uint8_t *decBuffer;
+ uint8_t decData;
+ uint32_t decBufferSize;
+ const uint8_t *end;
+} bufferInfo;
+
+typedef struct h264_decode_t {
+ uint8_t profile;
+ uint8_t level_idc;
+ uint8_t nal_ref_idc;
+ uint8_t nal_unit_type;
+ uint32_t pic_width, pic_height;
+ uint32_t slice_type;
+} h264_decode;
+
static amdgpu_device_handle device_handle;
static uint32_t major_version;
static uint32_t minor_version;
@@ -60,18 +164,33 @@
static uint32_t chip_id;
static uint32_t asic_id;
static uint32_t chip_rev;
-static uint32_t chip_id;
+static struct amdgpu_vcn_bo enc_buf;
+static struct amdgpu_vcn_bo cpb_buf;
+static uint32_t enc_task_id;
static amdgpu_context_handle context_handle;
static amdgpu_bo_handle ib_handle;
static amdgpu_va_handle ib_va_handle;
static uint64_t ib_mc_address;
static uint32_t *ib_cpu;
+static uint32_t *ib_checksum;
+static uint32_t *ib_size_in_dw;
+
+static rvcn_decode_buffer_t *decode_buffer;
static amdgpu_bo_handle resources[MAX_RESOURCES];
static unsigned num_resources;
-static struct amdgpu_vcn_reg reg;
+static uint8_t vcn_reg_index;
+static struct amdgpu_vcn_reg reg[] = {
+ {0x81c4, 0x81c5, 0x81c3, 0x81ff, 0x81c6},
+ {0x504, 0x505, 0x503, 0x53f, 0x506},
+ {0x10, 0x11, 0xf, 0x29, 0x26d},
+};
+
+uint32_t gWidth, gHeight, gSliceType;
+static uint32_t vcn_ip_version_major;
+static uint32_t vcn_ip_version_minor;
static void amdgpu_cs_vcn_dec_create(void);
static void amdgpu_cs_vcn_dec_decode(void);
static void amdgpu_cs_vcn_dec_destroy(void);
@@ -80,6 +199,22 @@
static void amdgpu_cs_vcn_enc_encode(void);
static void amdgpu_cs_vcn_enc_destroy(void);
+static void amdgpu_cs_sq_head(uint32_t *base, int *offset, bool enc);
+static void amdgpu_cs_sq_ib_tail(uint32_t *end);
+static void h264_check_0s (bufferInfo * bufInfo, int count);
+static int32_t h264_se (bufferInfo * bufInfo);
+static inline uint32_t bs_read_u1(bufferInfo *bufinfo);
+static inline int bs_eof(bufferInfo *bufinfo);
+static inline uint32_t bs_read_u(bufferInfo* bufinfo, int n);
+static inline uint32_t bs_read_ue(bufferInfo* bufinfo);
+static uint32_t remove_03 (uint8_t *bptr, uint32_t len);
+static void scaling_list (uint32_t ix, uint32_t sizeOfScalingList, bufferInfo *bufInfo);
+static void h264_parse_sequence_parameter_set (h264_decode * dec, bufferInfo *bufInfo);
+static void h264_slice_header (h264_decode *dec, bufferInfo *bufInfo);
+static uint8_t h264_parse_nal (h264_decode *dec, bufferInfo *bufInfo);
+static uint32_t h264_find_next_start_code (uint8_t *pBuf, uint32_t bufLen);
+static int verify_checksum(uint8_t *buffer, uint32_t buffer_size);
+
CU_TestInfo vcn_tests[] = {
{ "VCN DEC create", amdgpu_cs_vcn_dec_create },
@@ -87,7 +222,7 @@
{ "VCN DEC destroy", amdgpu_cs_vcn_dec_destroy },
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/drmdevice.c
^
|
| @@ -142,7 +142,7 @@
for (int j = 0; j < DRM_NODE_MAX; j++) {
if (devices[i]->available_nodes & 1 << j) {
printf("--- Opening device node %s ---\n", devices[i]->nodes[j]);
- fd = open(devices[i]->nodes[j], O_RDONLY | O_CLOEXEC, 0);
+ fd = open(devices[i]->nodes[j], O_RDONLY | O_CLOEXEC);
if (fd < 0) {
printf("Failed - %s (%d)\n", strerror(errno), errno);
continue;
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/exynos/exynos_fimg2d_test.c
^
|
| @@ -35,7 +35,6 @@
#include <xf86drm.h>
#include <xf86drmMode.h>
-#include <libkms.h>
#include <drm_fourcc.h>
#include "exynos_drm.h"
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/exynos/meson.build
^
|
| @@ -20,18 +20,15 @@
inc_exynos = include_directories('../../exynos')
-if with_libkms
- exynos_fimg2d_test = executable(
- 'exynos_fimg2d_test',
- files('exynos_fimg2d_test.c'),
- c_args : libdrm_c_args,
- include_directories : [inc_root, inc_drm, inc_exynos,
- include_directories('../../libkms')],
- link_with : [libdrm, libkms, libdrm_exynos],
- dependencies : dep_threads,
- install : with_install_tests,
- )
-endif
+exynos_fimg2d_test = executable(
+ 'exynos_fimg2d_test',
+ files('exynos_fimg2d_test.c'),
+ c_args : libdrm_c_args,
+ include_directories : [inc_root, inc_drm, inc_exynos],
+ link_with : [libdrm, libdrm_exynos],
+ dependencies : dep_threads,
+ install : with_install_tests,
+)
exynos_fimg2d_perf = executable(
'exynos_fimg2d_perf',
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/meson.build
^
|
| @@ -21,14 +21,10 @@
inc_tests = include_directories('.')
subdir('util')
-subdir('kms')
subdir('modeprint')
subdir('proptest')
subdir('modetest')
subdir('vbltest')
-if with_libkms
- subdir('kmstest')
-endif
if with_radeon
subdir('radeon')
endif
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/modeprint/modeprint.c
^
|
| @@ -113,7 +113,7 @@
} else {
for (j = 0; j < props->count_enums; j++) {
- printf("\t\t%" PRId64 " = %s\n", props->enums[j].value, props->enums[j].name);
+ printf("\t\t%" PRIu64" = %s\n", (uint64_t)props->enums[j].value, props->enums[j].name);
if (props->enums[j].value == value)
name = props->enums[j].name;
}
@@ -135,7 +135,7 @@
drmModePropertyPtr props;
const char *connector_type_name = NULL;
- connector_type_name = util_lookup_connector_type_name(connector->connector_type);
+ connector_type_name = drmModeGetConnectorTypeName(connector->connector_type);
if (connector_type_name)
printf("Connector: %s-%d\n", connector_type_name,
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/modetest/buffers.c
^
|
| @@ -37,6 +37,7 @@
#include "libdrm_macros.h"
#include "xf86drm.h"
+#include "xf86drmMode.h"
#include "buffers.h"
@@ -44,10 +45,9 @@
{
int fd;
void *ptr;
- size_t size;
- size_t offset;
- size_t pitch;
- unsigned handle;
+ uint64_t size;
+ uint32_t pitch;
+ uint32_t handle;
};
/* -----------------------------------------------------------------------------
@@ -57,7 +57,6 @@
static struct bo *
bo_create_dumb(int fd, unsigned int width, unsigned int height, unsigned int bpp)
{
- struct drm_mode_create_dumb arg;
struct bo *bo;
int ret;
@@ -67,12 +66,8 @@
return NULL;
}
- memset(&arg, 0, sizeof(arg));
- arg.bpp = bpp;
- arg.width = width;
- arg.height = height;
-
- ret = drmIoctl(fd, DRM_IOCTL_MODE_CREATE_DUMB, &arg);
+ ret = drmModeCreateDumbBuffer(fd, width, height, bpp, 0, &bo->handle,
+ &bo->pitch, &bo->size);
if (ret) {
fprintf(stderr, "failed to create dumb buffer: %s\n",
strerror(errno));
@@ -81,28 +76,22 @@
}
bo->fd = fd;
- bo->handle = arg.handle;
- bo->size = arg.size;
- bo->pitch = arg.pitch;
return bo;
}
static int bo_map(struct bo *bo, void **out)
{
- struct drm_mode_map_dumb arg;
void *map;
int ret;
+ uint64_t offset;
- memset(&arg, 0, sizeof(arg));
- arg.handle = bo->handle;
-
- ret = drmIoctl(bo->fd, DRM_IOCTL_MODE_MAP_DUMB, &arg);
+ ret = drmModeMapDumbBuffer(bo->fd, bo->handle, &offset);
if (ret)
return ret;
map = drm_mmap(0, bo->size, PROT_READ | PROT_WRITE, MAP_SHARED,
- bo->fd, arg.offset);
+ bo->fd, offset);
if (map == MAP_FAILED)
return -EINVAL;
@@ -340,13 +329,9 @@
void bo_destroy(struct bo *bo)
{
- struct drm_mode_destroy_dumb arg;
int ret;
- memset(&arg, 0, sizeof(arg));
- arg.handle = bo->handle;
-
- ret = drmIoctl(bo->fd, DRM_IOCTL_MODE_DESTROY_DUMB, &arg);
+ ret = drmModeDestroyDumbBuffer(bo->fd, bo->handle);
if (ret)
fprintf(stderr, "failed to destroy dumb buffer: %s\n",
strerror(errno));
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/modetest/modetest.c
^
|
| @@ -187,11 +187,9 @@
static void dump_fourcc(uint32_t fourcc)
{
- printf(" %c%c%c%c",
- fourcc,
- fourcc >> 8,
- fourcc >> 16,
- fourcc >> 24);
+ char *name = drmGetFormatName(fourcc);
+ printf(" %s", name);
+ free(name);
}
static void dump_encoders(struct device *dev)
@@ -376,7 +374,7 @@
printf("\t\tenums:");
for (i = 0; i < prop->count_enums; i++)
printf(" %s=%"PRIu64, prop->enums[i].name,
- prop->enums[i].value);
+ (uint64_t)prop->enums[i].value);
printf("\n");
} else if (drm_property_type_is(prop, DRM_MODE_PROP_BITMASK)) {
printf("\t\tvalues:");
@@ -656,7 +654,7 @@
int num;
num = asprintf(&connector->name, "%s-%u",
- util_lookup_connector_type_name(conn->connector_type),
+ drmModeGetConnectorTypeName(conn->connector_type),
conn->connector_type_id);
if (num < 0)
goto error;
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/proptest/proptest.c
^
|
| @@ -127,7 +127,7 @@
printf("\t\tenums:");
for (i = 0; i < prop->count_enums; i++)
printf(" %s=%"PRIu64, prop->enums[i].name,
- prop->enums[i].value);
+ (uint64_t)prop->enums[i].value);
printf("\n");
} else if (drm_property_type_is(prop, DRM_MODE_PROP_BITMASK)) {
printf("\t\tvalues:");
@@ -192,7 +192,7 @@
}
printf("Connector %u (%s-%u)\n", c->connector_id,
- util_lookup_connector_type_name(c->connector_type),
+ drmModeGetConnectorTypeName(c->connector_type),
c->connector_type_id);
listObjectProperties(c->connector_id,
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/tegra/.gitignore
^
|
| @@ -1 +1,2 @@
-openclose
+tegra-gr2d-fill
+tegra-openclose
|
|
[-]
[+]
|
Added |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/tegra/drm-test-tegra.c
^
|
| @@ -0,0 +1,147 @@
+/*
+ * Copyright © 2014 NVIDIA Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifdef HAVE_CONFIG_H
+# include "config.h"
+#endif
+
+#include <errno.h>
+#include <stdio.h>
+
+#include "drm-test-tegra.h"
+#include "tegra.h"
+
+int drm_tegra_gr2d_open(struct drm_tegra *drm, struct drm_tegra_gr2d **gr2dp)
+{
+ struct drm_tegra_gr2d *gr2d;
+ int err;
+
+ gr2d = calloc(1, sizeof(*gr2d));
+ if (!gr2d)
+ return -ENOMEM;
+
+ gr2d->drm = drm;
+
+ err = drm_tegra_channel_open(drm, DRM_TEGRA_GR2D, &gr2d->channel);
+ if (err < 0) {
+ free(gr2d);
+ return err;
+ }
+
+ *gr2dp = gr2d;
+
+ return 0;
+}
+
+int drm_tegra_gr2d_close(struct drm_tegra_gr2d *gr2d)
+{
+ if (!gr2d)
+ return -EINVAL;
+
+ drm_tegra_channel_close(gr2d->channel);
+ free(gr2d);
+
+ return 0;
+}
+
+int drm_tegra_gr2d_fill(struct drm_tegra_gr2d *gr2d, struct drm_framebuffer *fb,
+ unsigned int x, unsigned int y, unsigned int width,
+ unsigned int height, uint32_t color)
+{
+ struct drm_tegra_bo *fbo = fb->data;
+ struct drm_tegra_pushbuf *pushbuf;
+ struct drm_tegra_mapping *map;
+ struct drm_tegra_job *job;
+ uint32_t *ptr;
+ int err;
+
+ err = drm_tegra_job_new(gr2d->channel, &job);
+ if (err < 0)
+ return err;
+
+ err = drm_tegra_channel_map(gr2d->channel, fbo, 0, &map);
+ if (err < 0)
+ return err;
+
+ err = drm_tegra_job_get_pushbuf(job, &pushbuf);
+ if (err < 0)
+ return err;
+
+ err = drm_tegra_pushbuf_begin(pushbuf, 32, &ptr);
+ if (err < 0)
+ return err;
+
+ *ptr++ = HOST1X_OPCODE_SETCL(0, HOST1X_CLASS_GR2D, 0);
+
+ *ptr++ = HOST1X_OPCODE_MASK(0x9, 0x9);
+ *ptr++ = 0x0000003a;
+ *ptr++ = 0x00000000;
+
+ *ptr++ = HOST1X_OPCODE_MASK(0x1e, 0x7);
+ *ptr++ = 0x00000000;
+ *ptr++ = (2 << 16) | (1 << 6) | (1 << 2);
+ *ptr++ = 0x000000cc;
+
+ *ptr++ = HOST1X_OPCODE_MASK(0x2b, 0x9);
+
+ /* relocate destination buffer */
+ err = drm_tegra_pushbuf_relocate(pushbuf, &ptr, map, 0, 0, 0);
+ if (err < 0) {
+ fprintf(stderr, "failed to relocate buffer object: %d\n", err);
+ return err;
+ }
+
+ *ptr++ = fb->pitch;
+
+ *ptr++ = HOST1X_OPCODE_NONINCR(0x35, 1);
+ *ptr++ = color;
+
+ *ptr++ = HOST1X_OPCODE_NONINCR(0x46, 1);
+ *ptr++ = 0x00000000;
+
+ *ptr++ = HOST1X_OPCODE_MASK(0x38, 0x5);
+ *ptr++ = height << 16 | width;
+ *ptr++ = y << 16 | x;
+
+ err = drm_tegra_pushbuf_end(pushbuf, ptr);
+ if (err < 0) {
+ fprintf(stderr, "failed to update push buffer: %d\n", -err);
+ return err;
+ }
+
+ err = drm_tegra_job_submit(job, NULL);
+ if (err < 0) {
+ fprintf(stderr, "failed to submit job: %d\n", err);
+ return err;
+ }
+
+ err = drm_tegra_job_wait(job, 0);
+ if (err < 0) {
+ fprintf(stderr, "failed to wait for fence: %d\n", err);
+ return err;
+ }
+
+ drm_tegra_channel_unmap(map);
+ drm_tegra_job_free(job);
+
+ return 0;
+}
|
|
[-]
[+]
|
Added |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/tegra/drm-test-tegra.h
^
|
| @@ -0,0 +1,55 @@
+/*
+ * Copyright © 2014 NVIDIA Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef TEGRA_DRM_TEST_TEGRA_H
+#define TEGRA_DRM_TEST_TEGRA_H
+
+#include "drm-test.h"
+#include "tegra.h"
+
+#define HOST1X_OPCODE_SETCL(offset, classid, mask) \
+ ((0x0 << 28) | (((offset) & 0xfff) << 16) | (((classid) & 0x3ff) << 6) | ((mask) & 0x3f))
+#define HOST1X_OPCODE_INCR(offset, count) \
+ ((0x1 << 28) | (((offset) & 0xfff) << 16) | ((count) & 0xffff))
+#define HOST1X_OPCODE_NONINCR(offset, count) \
+ ((0x2 << 28) | (((offset) & 0xfff) << 16) | ((count) & 0xffff))
+#define HOST1X_OPCODE_MASK(offset, mask) \
+ ((0x3 << 28) | (((offset) & 0xfff) << 16) | ((mask) & 0xffff))
+#define HOST1X_OPCODE_IMM(offset, data) \
+ ((0x4 << 28) | (((offset) & 0xfff) << 16) | ((data) & 0xffff))
+#define HOST1X_OPCODE_EXTEND(subop, value) \
+ ((0xe << 28) | (((subop) & 0xf) << 24) | ((value) & 0xffffff))
+
+#define HOST1X_CLASS_GR2D 0x51
+
+struct drm_tegra_gr2d {
+ struct drm_tegra *drm;
+ struct drm_tegra_channel *channel;
+};
+
+int drm_tegra_gr2d_open(struct drm_tegra *drm, struct drm_tegra_gr2d **gr2dp);
+int drm_tegra_gr2d_close(struct drm_tegra_gr2d *gr2d);
+int drm_tegra_gr2d_fill(struct drm_tegra_gr2d *gr2d, struct drm_framebuffer *fb,
+ unsigned int x, unsigned int y, unsigned int width,
+ unsigned int height, uint32_t color);
+
+#endif
|
|
[-]
[+]
|
Added |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/tegra/drm-test.c
^
|
| @@ -0,0 +1,248 @@
+/*
+ * Copyright © 2014 NVIDIA Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifdef HAVE_CONFIG_H
+# include "config.h"
+#endif
+
+#include <errno.h>
+#include <fcntl.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+#include <sys/ioctl.h>
+
+#include "xf86drm.h"
+#include "xf86drmMode.h"
+#include "drm_fourcc.h"
+
+#include "drm-test.h"
+
+static int drm_screen_probe_connector(struct drm_screen *screen,
+ drmModeConnectorPtr connector)
+{
+ drmModeEncoderPtr encoder;
+ drmModeCrtcPtr crtc;
+ drmModeFBPtr fb;
+
+ encoder = drmModeGetEncoder(screen->fd, connector->encoder_id);
+ if (!encoder)
+ return -ENODEV;
+
+ crtc = drmModeGetCrtc(screen->fd, encoder->crtc_id);
+ if (!crtc) {
+ drmModeFreeEncoder(encoder);
+ return -ENODEV;
+ }
+
+ screen->old_fb = crtc->buffer_id;
+
+ fb = drmModeGetFB(screen->fd, crtc->buffer_id);
+ if (!fb) {
+ /* TODO: create new framebuffer */
+ drmModeFreeEncoder(encoder);
+ drmModeFreeCrtc(crtc);
+ return -ENOSYS;
+ }
+
+ screen->connector = connector->connector_id;
+ screen->old_fb = crtc->buffer_id;
+ screen->crtc = encoder->crtc_id;
+ /* TODO: check crtc->mode_valid */
+ screen->mode = crtc->mode;
+
+ screen->width = fb->width;
+ screen->height = fb->height;
+ screen->pitch = fb->pitch;
+ screen->depth = fb->depth;
+ screen->bpp = fb->bpp;
+
+ drmModeFreeEncoder(encoder);
+ drmModeFreeCrtc(crtc);
+ drmModeFreeFB(fb);
+
+ return 0;
+}
+
+int drm_screen_open(struct drm_screen **screenp, int fd)
+{
+ drmModeConnectorPtr connector;
+ struct drm_screen *screen;
+ bool found = false;
+ drmModeResPtr res;
+ unsigned int i;
+ int err;
+
+ if (!screenp || fd < 0)
+ return -EINVAL;
+
+ screen = calloc(1, sizeof(*screen));
+ if (!screen)
+ return -ENOMEM;
+
+ screen->format = DRM_FORMAT_XRGB8888;
+ screen->fd = fd;
+
+ res = drmModeGetResources(fd);
+ if (!res) {
+ free(screen);
+ return -ENOMEM;
+ }
+
+ for (i = 0; i < (unsigned int)res->count_connectors; i++) {
+ connector = drmModeGetConnector(fd, res->connectors[i]);
+ if (!connector)
+ continue;
+
+ if (connector->connection != DRM_MODE_CONNECTED) {
+ drmModeFreeConnector(connector);
+ continue;
+ }
+
+ err = drm_screen_probe_connector(screen, connector);
+ if (err < 0) {
+ drmModeFreeConnector(connector);
+ continue;
+ }
+
+ drmModeFreeConnector(connector);
+ found = true;
+ break;
+ }
+
+ drmModeFreeResources(res);
+
+ if (!found) {
+ free(screen);
+ return -ENODEV;
+ }
+
+ *screenp = screen;
+
+ return 0;
+}
+
+int drm_screen_close(struct drm_screen *screen)
+{
+ int err;
+
+ err = drmModeSetCrtc(screen->fd, screen->crtc, screen->old_fb, 0, 0,
+ &screen->connector, 1, &screen->mode);
+ if (err < 0) {
+ fprintf(stderr, "drmModeSetCrtc() failed: %m\n");
+ return -errno;
+ }
+
+ free(screen);
+
+ return 0;
+}
+
+int drm_framebuffer_new(struct drm_framebuffer **fbp,
+ struct drm_screen *screen, uint32_t handle,
+ unsigned int width, unsigned int height,
+ unsigned int pitch, uint32_t format,
+ void *data)
+{
+ struct drm_framebuffer *fb;
+ uint32_t handles[4];
+ uint32_t pitches[4];
+ uint32_t offsets[4];
+ int err;
+
+ fb = calloc(1, sizeof(*fb));
+ if (!fb)
+ return -ENOMEM;
+
+ fb->fd = screen->fd;
+ fb->width = width;
+ fb->height = height;
+ fb->pitch = pitch;
+ fb->format = format;
+ fb->data = data;
+
+ handles[0] = handle;
+ pitches[0] = pitch;
+ offsets[0] = 0;
+
+ err = drmModeAddFB2(screen->fd, width, height, format, handles,
+ pitches, offsets, &fb->handle, 0);
+ if (err < 0)
+ return -errno;
+
+ *fbp = fb;
+
+ return 0;
+}
|
|
[-]
[+]
|
Added |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/tegra/drm-test.h
^
|
| @@ -0,0 +1,72 @@
+/*
+ * Copyright © 2014 NVIDIA Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef TEGRA_DRM_TEST_H
+#define TEGRA_DRM_TEST_H
+
+#include <stdint.h>
+#include <stdlib.h>
+
+#include "xf86drmMode.h"
+
+struct drm_screen {
+ int fd;
+
+ unsigned int width;
+ unsigned int height;
+ unsigned int pitch;
+ unsigned int depth;
+ unsigned int bpp;
+
+ drmModeModeInfo mode;
+ uint32_t connector;
+ uint32_t old_fb;
+ uint32_t format;
+ uint32_t crtc;
+};
+
+struct drm_framebuffer {
+ unsigned int width;
+ unsigned int height;
+ unsigned int pitch;
+ uint32_t format;
+ uint32_t handle;
+ void *data;
+ int fd;
+};
+
+int drm_screen_open(struct drm_screen **screenp, int fd);
+int drm_screen_close(struct drm_screen *screen);
+int drm_screen_set_framebuffer(struct drm_screen *screen,
+ struct drm_framebuffer *fb);
+
+int drm_framebuffer_new(struct drm_framebuffer **fbp,
+ struct drm_screen *screen, uint32_t handle,
+ unsigned int width, unsigned int height,
+ unsigned int pitch, uint32_t format,
+ void *data);
+int drm_framebuffer_free(struct drm_framebuffer *fb);
+
+int drm_open(const char *path);
+void drm_close(int fd);
+
+#endif
|
|
[-]
[+]
|
Added |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/tegra/gr2d-fill.c
^
|
| @@ -0,0 +1,146 @@
+/*
+ * Copyright © 2014 NVIDIA Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifdef HAVE_CONFIG_H
+# include "config.h"
+#endif
+
+#include <errno.h>
+#include <fcntl.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+#include <sys/ioctl.h>
+
+#include "xf86drm.h"
+#include "xf86drmMode.h"
+#include "drm_fourcc.h"
+
+#include "drm-test-tegra.h"
+#include "tegra.h"
+
+int main(int argc, char *argv[])
+{
+ uint32_t format = DRM_FORMAT_XRGB8888;
+ struct drm_tegra_gr2d *gr2d;
+ struct drm_framebuffer *fb;
+ struct drm_screen *screen;
+ unsigned int pitch, size;
+ struct drm_tegra_bo *bo;
+ struct drm_tegra *drm;
+ uint32_t handle;
+ int fd, err;
+ void *ptr;
+
+ fd = drm_open(argv[1]);
+ if (fd < 0) {
+ fprintf(stderr, "failed to open DRM device %s: %s\n", argv[1],
+ strerror(errno));
+ return 1;
+ }
+
+ err = drm_screen_open(&screen, fd);
+ if (err < 0) {
+ fprintf(stderr, "failed to open screen: %s\n", strerror(-err));
+ return 1;
+ }
+
+ err = drm_tegra_new(fd, &drm);
+ if (err < 0) {
+ fprintf(stderr, "failed to create Tegra DRM context: %s\n",
+ strerror(-err));
+ return 1;
+ }
+
+ err = drm_tegra_gr2d_open(drm, &gr2d);
+ if (err < 0) {
+ fprintf(stderr, "failed to open gr2d channel: %s\n",
+ strerror(-err));
+ return 1;
+ }
+
+ pitch = screen->width * screen->bpp / 8;
+ size = pitch * screen->height;
+
+ err = drm_tegra_bo_new(drm, 0, size, &bo);
+ if (err < 0) {
+ fprintf(stderr, "failed to create buffer object: %s\n",
+ strerror(-err));
+ return 1;
+ }
+
+ err = drm_tegra_bo_get_handle(bo, &handle);
+ if (err < 0) {
+ fprintf(stderr, "failed to get handle to buffer object: %s\n",
+ strerror(-err));
+ return 1;
+ }
+
+ err = drm_tegra_bo_map(bo, &ptr);
+ if (err < 0) {
+ fprintf(stderr, "failed to map buffer object: %s\n",
+ strerror(-err));
+ return 1;
+ }
+
+ memset(ptr, 0xff, size);
+
+ err = drm_framebuffer_new(&fb, screen, handle, screen->width,
+ screen->height, pitch, format, bo);
+ if (err < 0) {
+ fprintf(stderr, "failed to create framebuffer: %s\n",
+ strerror(-err));
+ return 1;
+ }
+
+ err = drm_screen_set_framebuffer(screen, fb);
+ if (err < 0) {
+ fprintf(stderr, "failed to display framebuffer: %s\n",
+ strerror(-err));
+ return 1;
+ }
+
+ sleep(1);
+
+ err = drm_tegra_gr2d_fill(gr2d, fb, fb->width / 4, fb->height / 4,
+ fb->width / 2, fb->height / 2, 0x00000000);
+ if (err < 0) {
+ fprintf(stderr, "failed to fill rectangle: %s\n",
+ strerror(-err));
+ return 1;
+ }
+
+ sleep(1);
+
+ drm_framebuffer_free(fb);
+ drm_tegra_bo_unref(bo);
+ drm_tegra_gr2d_close(gr2d);
+ drm_tegra_close(drm);
+ drm_screen_close(screen);
+ drm_close(fd);
+
+ return 0;
+}
|
|
[-]
[+]
|
Added |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/tegra/host1x.h
^
|
| @@ -0,0 +1,34 @@
+/*
+ * Copyright © 2018 NVIDIA Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef HOST1X_H
+#define HOST1X_H
+
+#define HOST1X_OPCODE_SETCL(offset, classid, mask) \
+ ((0x0 << 28) | (((offset) & 0xfff) << 16) | (((classid) & 0x3ff) << 6) | ((mask) & 0x3f))
+
+#define HOST1X_OPCODE_INCR(offset, count) \
+ ((0x1 << 28) | (((offset) & 0xfff) << 16) | ((count) & 0xffff))
+
+#define HOST1X_CLASS_VIC 0x5d
+
+#endif
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/tegra/meson.build
^
|
| @@ -18,10 +18,94 @@
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
+inc_tegra = include_directories('../../tegra')
+
+libdrm_test = static_library(
+ 'drm-test',
+ [files('drm-test.c', 'drm-test.h'), config_file ],
+ include_directories : [inc_root, inc_drm, inc_tegra],
+ link_with : libdrm,
+)
+
+libdrm_test_tegra = static_library(
+ 'drm-test-tegra',
+ [files(
+ 'drm-test-tegra.c',
+ 'drm-test-tegra.h',
+ 'vic.c',
+ 'vic.h',
+ 'vic30.c',
+ 'vic30.h',
+ 'vic40.c',
+ 'vic40.h',
+ 'vic41.c',
+ 'vic41.h',
+ 'vic42.c',
+ 'vic42.h',
+ ), config_file ],
+ include_directories : [inc_root, inc_drm, inc_tegra],
+ link_with : libdrm,
+)
+
openclose = executable(
- 'openclose',
+ 'tegra-openclose',
files('openclose.c'),
- include_directories : [inc_root, inc_drm, include_directories('../../tegra')],
+ include_directories : [inc_root, inc_drm, inc_tegra],
c_args : libdrm_c_args,
link_with : [libdrm, libdrm_tegra],
+ install : with_install_tests,
+)
+
+gr2d_fill = executable(
+ 'tegra-gr2d-fill',
+ files('gr2d-fill.c'),
+ include_directories : [inc_root, inc_drm, inc_tegra],
+ c_args : libdrm_c_args,
+ link_with : [libdrm, libdrm_tegra, libdrm_test, libdrm_test_tegra],
+ install : with_install_tests,
+)
+
+syncpt_wait = executable(
+ 'tegra-syncpt-wait',
+ files('syncpt-wait.c'),
+ include_directories : [inc_root, inc_drm, inc_tegra],
+ c_args : libdrm_c_args,
+ link_with : [libdrm, libdrm_tegra, libdrm_test, libdrm_test_tegra],
+ install : with_install_tests,
+)
+
+syncpt_timeout = executable(
+ 'tegra-syncpt-timeout',
+ files('syncpt-timeout.c'),
+ include_directories : [inc_root, inc_drm, inc_tegra],
+ c_args : libdrm_c_args,
+ link_with : [libdrm, libdrm_tegra, libdrm_test, libdrm_test_tegra],
+ install : with_install_tests,
+)
+
+vic_clear = executable(
+ 'tegra-vic-clear',
+ files('vic-clear.c'),
+ include_directories : [inc_root, inc_drm, inc_tegra],
+ c_args : libdrm_c_args,
+ link_with : [libdrm, libdrm_tegra, libdrm_test, libdrm_test_tegra],
+ install : with_install_tests,
+)
+
+vic_blit = executable(
+ 'tegra-vic-blit',
+ files('vic-blit.c'),
+ include_directories : [inc_root, inc_drm, inc_tegra],
+ c_args : libdrm_c_args,
+ link_with : [libdrm, libdrm_tegra, libdrm_test, libdrm_test_tegra],
+ install : with_install_tests,
+)
+
+vic_flip = executable(
+ 'tegra-vic-flip',
+ files('vic-flip.c'),
+ include_directories : [inc_root, inc_drm, inc_tegra],
+ c_args : libdrm_c_args,
+ link_with : [libdrm, libdrm_tegra, libdrm_test, libdrm_test_tegra],
+ install : with_install_tests,
)
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/tegra/openclose.c
^
|
| @@ -31,37 +31,37 @@
int main(int argc, char *argv[])
{
- struct drm_tegra *tegra;
- drmVersionPtr version;
- const char *device;
- int err, fd;
-
- if (argc < 2)
- device = default_device;
- else
- device = argv[1];
-
- fd = open(device, O_RDWR);
- if (fd < 0)
- return 1;
-
- version = drmGetVersion(fd);
- if (version) {
- printf("Version: %d.%d.%d\n", version->version_major,
- version->version_minor, version->version_patchlevel);
- printf(" Name: %s\n", version->name);
- printf(" Date: %s\n", version->date);
- printf(" Description: %s\n", version->desc);
-
- drmFreeVersion(version);
- }
-
- err = drm_tegra_new(&tegra, fd);
- if (err < 0)
- return 1;
+ struct drm_tegra *tegra;
+ drmVersionPtr version;
+ const char *device;
+ int err, fd;
+
+ if (argc < 2)
+ device = default_device;
+ else
+ device = argv[1];
+
+ fd = open(device, O_RDWR);
+ if (fd < 0)
+ return 1;
+
+ version = drmGetVersion(fd);
+ if (version) {
+ printf("Version: %d.%d.%d\n", version->version_major,
+ version->version_minor, version->version_patchlevel);
+ printf(" Name: %s\n", version->name);
+ printf(" Date: %s\n", version->date);
+ printf(" Description: %s\n", version->desc);
+
+ drmFreeVersion(version);
+ }
+
+ err = drm_tegra_new(fd, &tegra);
+ if (err < 0)
+ return 1;
- drm_tegra_close(tegra);
- close(fd);
+ drm_tegra_close(tegra);
+ close(fd);
- return 0;
+ return 0;
}
|
|
[-]
[+]
|
Added |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/tegra/syncpt-timeout.c
^
|
| @@ -0,0 +1,163 @@
+/*
+ * Copyright © 2018 NVIDIA Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <errno.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <string.h>
+#include <unistd.h>
+
+#include "tegra.h"
+
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
+
+static int channel_open(struct drm_tegra *drm,
+ struct drm_tegra_channel **channel)
+{
+ static const struct {
+ enum drm_tegra_class class;
+ const char *name;
+ } classes[] = {
+ { DRM_TEGRA_VIC, "VIC" },
+ { DRM_TEGRA_GR2D, "GR2D" },
+ };
+ unsigned int i;
+ int err;
+
+ for (i = 0; i < ARRAY_SIZE(classes); i++) {
+ err = drm_tegra_channel_open(drm, classes[i].class, channel);
+ if (err < 0) {
+ fprintf(stderr, "failed to open channel to %s: %s\n",
+ classes[i].name, strerror(-err));
+ continue;
+ }
+
+ break;
+ }
+
+ return err;
+}
+
+int main(int argc, char *argv[])
+{
+ const char *device = "/dev/dri/renderD128";
+ struct drm_tegra_syncpoint *syncpt;
+ struct drm_tegra_channel *channel;
+ struct drm_tegra_pushbuf *pushbuf;
+ struct drm_tegra_job *job;
+ struct drm_tegra *drm;
+ uint32_t *ptr;
+ int fd, err;
+
+ if (argc > 1)
+ device = argv[1];
+
+ fd = open(device, O_RDWR);
+ if (fd < 0) {
+ fprintf(stderr, "open() failed: %s\n", strerror(errno));
+ return 1;
+ }
+
+ err = drm_tegra_new(fd, &drm);
+ if (err < 0) {
+ fprintf(stderr, "failed to open Tegra device: %s\n", strerror(-err));
+ close(fd);
+ return 1;
+ }
+
+ err = drm_tegra_syncpoint_new(drm, &syncpt);
+ if (err < 0) {
+ fprintf(stderr, "failed to allocate syncpoint: %s\n", strerror(-err));
+ drm_tegra_close(drm);
+ close(fd);
+ return 1;
+ }
+
+ err = channel_open(drm, &channel);
+ if (err < 0) {
+ fprintf(stderr, "failed to open channel: %s\n", strerror(-err));
+ return 1;
+ }
+
+ err = drm_tegra_job_new(channel, &job);
+ if (err < 0) {
+ fprintf(stderr, "failed to create job: %s\n", strerror(-err));
+ return 1;
+ }
+
+ err = drm_tegra_job_get_pushbuf(job, &pushbuf);
+ if (err < 0) {
+ fprintf(stderr, "failed to create push buffer: %s\n", strerror(-err));
+ return 1;
+ }
+
+ err = drm_tegra_pushbuf_begin(pushbuf, 8, &ptr);
+ if (err < 0) {
+ fprintf(stderr, "failed to prepare push buffer: %s\n", strerror(-err));
+ return 1;
+ }
+
+ /*
+ * Empty command streams will be rejected, so we use this as an easy way
+ * to add something to the command stream. But this could be any other,
+ * valid command stream.
+ */
+ err = drm_tegra_pushbuf_sync_cond(pushbuf, &ptr, syncpt,
+ DRM_TEGRA_SYNC_COND_IMMEDIATE);
+ if (err < 0) {
+ fprintf(stderr, "failed to push syncpoint: %s\n", strerror(-err));
+ return 1;
+ }
+
+ /* pretend that the syncpoint was incremented a second time */
+ err = drm_tegra_pushbuf_sync(pushbuf, syncpt, 1);
+ if (err < 0) {
+ fprintf(stderr, "failed to push syncpoint: %s\n", strerror(-err));
+ return 1;
+ }
+
+ err = drm_tegra_pushbuf_end(pushbuf, ptr);
+ if (err < 0) {
+ fprintf(stderr, "failed to update push buffer: %s\n", strerror(-err));
+ return 1;
+ }
+
+ err = drm_tegra_job_submit(job, NULL);
+ if (err < 0) {
+ fprintf(stderr, "failed to submit job: %s\n", strerror(-err));
+ return 1;
+ }
+
+ err = drm_tegra_job_wait(job, 250000);
+ if (err < 0) {
+ fprintf(stderr, "failed to wait for job: %s\n", strerror(-err));
+ return 1;
+ }
+
+ drm_tegra_job_free(job);
+ drm_tegra_channel_close(channel);
+ drm_tegra_syncpoint_free(syncpt);
+ drm_tegra_close(drm);
+ close(fd);
+
+ return 0;
+}
|
|
[-]
[+]
|
Added |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/tegra/syncpt-wait.c
^
|
| @@ -0,0 +1,151 @@
+/*
+ * Copyright © 2018 NVIDIA Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <errno.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <string.h>
+#include <unistd.h>
+
+#include "tegra.h"
+
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
+
+static int channel_open(struct drm_tegra *drm,
+ struct drm_tegra_channel **channel)
+{
+ static const struct {
+ enum drm_tegra_class class;
+ const char *name;
+ } classes[] = {
+ { DRM_TEGRA_VIC, "VIC" },
+ { DRM_TEGRA_GR2D, "GR2D" },
+ };
+ unsigned int i;
+ int err;
+
+ for (i = 0; i < ARRAY_SIZE(classes); i++) {
+ err = drm_tegra_channel_open(drm, classes[i].class, channel);
+ if (err < 0) {
+ fprintf(stderr, "failed to open channel to %s: %s\n",
+ classes[i].name, strerror(-err));
+ continue;
+ }
+
+ break;
+ }
+
+ return err;
+}
+
+int main(int argc, char *argv[])
+{
+ const char *device = "/dev/dri/renderD128";
+ struct drm_tegra_syncpoint *syncpt;
+ struct drm_tegra_channel *channel;
+ struct drm_tegra_pushbuf *pushbuf;
+ struct drm_tegra_job *job;
+ struct drm_tegra *drm;
+ uint32_t *ptr;
+ int fd, err;
+
+ if (argc > 1)
+ device = argv[1];
+
+ fd = open(device, O_RDWR);
+ if (fd < 0) {
+ fprintf(stderr, "open() failed: %s\n", strerror(errno));
+ return 1;
+ }
+
+ err = drm_tegra_new(fd, &drm);
+ if (err < 0) {
+ fprintf(stderr, "failed to open Tegra device: %s\n", strerror(-err));
+ close(fd);
+ return 1;
+ }
+
+ err = drm_tegra_syncpoint_new(drm, &syncpt);
+ if (err < 0) {
+ fprintf(stderr, "failed to allocate syncpoint: %s\n", strerror(-err));
+ drm_tegra_close(drm);
+ close(fd);
+ return 1;
+ }
+
+ err = channel_open(drm, &channel);
+ if (err < 0) {
+ fprintf(stderr, "failed to open channel: %s\n", strerror(-err));
+ return 1;
+ }
+
+ err = drm_tegra_job_new(channel, &job);
+ if (err < 0) {
+ fprintf(stderr, "failed to create job: %s\n", strerror(-err));
+ return 1;
+ }
+
+ err = drm_tegra_job_get_pushbuf(job, &pushbuf);
+ if (err < 0) {
+ fprintf(stderr, "failed to create push buffer: %s\n", strerror(-err));
+ return 1;
+ }
+
+ err = drm_tegra_pushbuf_begin(pushbuf, 4, &ptr);
+ if (err < 0) {
+ fprintf(stderr, "failed to prepare push buffer: %s\n", strerror(-err));
+ return 1;
+ }
+
+ err = drm_tegra_pushbuf_sync_cond(pushbuf, &ptr, syncpt,
+ DRM_TEGRA_SYNC_COND_IMMEDIATE);
+ if (err < 0) {
+ fprintf(stderr, "failed to push syncpoint: %s\n", strerror(-err));
+ return 1;
+ }
+
+ err = drm_tegra_pushbuf_end(pushbuf, ptr);
+ if (err < 0) {
+ fprintf(stderr, "failed to update push buffer: %s\n", strerror(-err));
+ return 1;
+ }
+
+ err = drm_tegra_job_submit(job, NULL);
+ if (err < 0) {
+ fprintf(stderr, "failed to submit job: %s\n", strerror(-err));
+ return 1;
+ }
+
+ err = drm_tegra_job_wait(job, 250000000);
+ if (err < 0) {
+ fprintf(stderr, "failed to wait for job: %s\n", strerror(-err));
+ return 1;
+ }
+
+ drm_tegra_job_free(job);
+ drm_tegra_channel_close(channel);
+ drm_tegra_syncpoint_free(syncpt);
+ drm_tegra_close(drm);
+ close(fd);
+
+ return 0;
+}
|
|
[-]
[+]
|
Added |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/tegra/vic-blit.c
^
|
| @@ -0,0 +1,333 @@
+/*
+ * Copyright © 2018 NVIDIA Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <errno.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <string.h>
+#include <unistd.h>
+
+#include "tegra.h"
+
+#include "host1x.h"
+#include "vic.h"
+
+/* clear output image to red */
+static int clear(struct vic *vic, struct drm_tegra_channel *channel,
+ struct vic_image *output)
+{
+ struct drm_tegra_pushbuf *pushbuf;
+ struct drm_tegra_job *job;
+ uint32_t *ptr;
+ int err;
+
+ err = drm_tegra_job_new(channel, &job);
+ if (err < 0) {
+ fprintf(stderr, "failed to create job: %s\n", strerror(-err));
+ return 1;
+ }
+
+ err = drm_tegra_job_get_pushbuf(job, &pushbuf);
+ if (err < 0) {
+ fprintf(stderr, "failed to create push buffer: %s\n", strerror(-err));
+ return 1;
+ }
+
+ err = vic_clear(vic, output, 1023, 1023, 0, 0);
+ if (err < 0) {
+ fprintf(stderr, "failed to clear surface: %s\n", strerror(-err));
+ return err;
+ }
+
+ err = drm_tegra_pushbuf_begin(pushbuf, 32, &ptr);
+ if (err < 0) {
+ fprintf(stderr, "failed to prepare push buffer: %s\n", strerror(-err));
+ return err;
+ }
+
+ err = vic->ops->execute(vic, pushbuf, &ptr, output, NULL, 0);
+ if (err < 0) {
+ fprintf(stderr, "failed to execute operation: %s\n", strerror(-err));
+ return err;
+ }
+
+ err = drm_tegra_pushbuf_sync_cond(pushbuf, &ptr, vic->syncpt,
+ DRM_TEGRA_SYNC_COND_OP_DONE);
+ if (err < 0) {
+ fprintf(stderr, "failed to push syncpoint: %s\n", strerror(-err));
+ return err;
+ }
+
+ err = drm_tegra_pushbuf_end(pushbuf, ptr);
+ if (err < 0) {
+ fprintf(stderr, "failed to update push buffer: %s\n", strerror(-err));
+ return err;
+ }
+
+ err = drm_tegra_job_submit(job, NULL);
+ if (err < 0) {
+ fprintf(stderr, "failed to submit job: %s\n", strerror(-err));
+ return err;
+ }
+
+ err = drm_tegra_job_wait(job, 1000000000);
+ if (err < 0) {
+ fprintf(stderr, "failed to wait for job: %s\n", strerror(-err));
+ return err;
+ }
+
+ drm_tegra_job_free(job);
+
+ return 0;
+}
+
+/* fill bottom half of image to blue */
+static int fill(struct vic *vic, struct drm_tegra_channel *channel,
+ struct vic_image *output)
+{
+ struct drm_tegra_pushbuf *pushbuf;
+ struct drm_tegra_job *job;
+ uint32_t *ptr;
+ int err;
+
+ err = drm_tegra_job_new(channel, &job);
+ if (err < 0) {
+ fprintf(stderr, "failed to create job: %s\n", strerror(-err));
+ return 1;
+ }
+
+ err = drm_tegra_job_get_pushbuf(job, &pushbuf);
+ if (err < 0) {
+ fprintf(stderr, "failed to create push buffer: %s\n", strerror(-err));
+ return 1;
+ }
+
+ err = drm_tegra_pushbuf_begin(pushbuf, 32, &ptr);
+ if (err < 0) {
+ fprintf(stderr, "failed to prepare push buffer: %s\n", strerror(-err));
+ return err;
+ }
+
+ err = vic->ops->fill(vic, output, 0, output->height / 2, output->width - 1,
+ output->height -1, 1023, 0, 0, 1023);
+ if (err < 0) {
+ fprintf(stderr, "failed to fill surface: %s\n", strerror(-err));
+ return err;
+ }
+
+ err = vic->ops->execute(vic, pushbuf, &ptr, output, NULL, 0);
+ if (err < 0) {
+ fprintf(stderr, "failed to execute operation: %s\n", strerror(-err));
+ return err;
+ }
+
+ err = drm_tegra_pushbuf_sync_cond(pushbuf, &ptr, vic->syncpt,
+ DRM_TEGRA_SYNC_COND_OP_DONE);
+ if (err < 0) {
+ fprintf(stderr, "failed to push syncpoint: %s\n", strerror(-err));
+ return err;
+ }
+
+ err = drm_tegra_pushbuf_end(pushbuf, ptr);
+ if (err < 0) {
+ fprintf(stderr, "failed to update push buffer: %s\n", strerror(-err));
+ return err;
+ }
+
+ err = drm_tegra_job_submit(job, NULL);
+ if (err < 0) {
+ fprintf(stderr, "failed to submit job: %s\n", strerror(-err));
+ return err;
+ }
+
+ err = drm_tegra_job_wait(job, 1000000000);
+ if (err < 0) {
+ fprintf(stderr, "failed to wait for job: %s\n", strerror(-err));
+ return err;
+ }
+
+ drm_tegra_job_free(job);
+
+ return 0;
+}
+
+/* blit image */
+static int blit(struct vic *vic, struct drm_tegra_channel *channel,
+ struct vic_image *output, struct vic_image *input)
+{
+ struct drm_tegra_pushbuf *pushbuf;
+ struct drm_tegra_job *job;
+ uint32_t *ptr;
+ int err;
+
+ err = drm_tegra_job_new(channel, &job);
+ if (err < 0) {
+ fprintf(stderr, "failed to create job: %s\n", strerror(-err));
+ return 1;
+ }
+
+ err = drm_tegra_job_get_pushbuf(job, &pushbuf);
+ if (err < 0) {
+ fprintf(stderr, "failed to create push buffer: %s\n", strerror(-err));
+ return 1;
+ }
+
+ err = drm_tegra_pushbuf_begin(pushbuf, 32, &ptr);
+ if (err < 0) {
+ fprintf(stderr, "failed to prepare push buffer: %s\n", strerror(-err));
+ return err;
+ }
+
|
|
[-]
[+]
|
Added |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/tegra/vic-clear.c
^
|
| @@ -0,0 +1,173 @@
+/*
+ * Copyright © 2018 NVIDIA Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <errno.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <string.h>
+#include <unistd.h>
+
+#include "util_math.h"
+
+#include "tegra.h"
+
+#include "host1x.h"
+#include "vic.h"
+
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
+
+int main(int argc, char *argv[])
+{
+ const unsigned int format = VIC_PIXEL_FORMAT_A8R8G8B8;
+ const unsigned int kind = VIC_BLK_KIND_PITCH;
+ const unsigned int width = 16, height = 16;
+ const char *device = "/dev/dri/renderD128";
+ struct drm_tegra_channel *channel;
+ struct drm_tegra_pushbuf *pushbuf;
+ struct drm_tegra_job *job;
+ struct vic_image *output;
+ struct drm_tegra *drm;
+ unsigned int version;
+ struct vic *vic;
+ uint32_t *pb;
+ int fd, err;
+ void *ptr;
+
+ if (argc > 1)
+ device = argv[1];
+
+ fd = open(device, O_RDWR);
+ if (fd < 0) {
+ fprintf(stderr, "open() failed: %s\n", strerror(errno));
+ return 1;
+ }
+
+ err = drm_tegra_new(fd, &drm);
+ if (err < 0) {
+ fprintf(stderr, "failed to open Tegra device: %s\n", strerror(-err));
+ close(fd);
+ return 1;
+ }
+
+ err = drm_tegra_channel_open(drm, DRM_TEGRA_VIC, &channel);
+ if (err < 0) {
+ fprintf(stderr, "failed to open channel to VIC: %s\n", strerror(-err));
+ return 1;
+ }
+
+ version = drm_tegra_channel_get_version(channel);
+ printf("version: %08x\n", version);
+
+ err = vic_new(drm, channel, &vic);
+ if (err < 0) {
+ fprintf(stderr, "failed to create VIC: %s\n", strerror(-err));
+ return 1;
+ }
+
+ err = vic_image_new(vic, width, height, format, kind, DRM_TEGRA_CHANNEL_MAP_READ_WRITE,
+ &output);
+ if (err < 0) {
+ fprintf(stderr, "failed to create output image: %d\n", err);
+ return 1;
+ }
+
+ printf("image: %zu bytes\n", output->size);
+
+ err = drm_tegra_bo_map(output->bo, &ptr);
+ if (err < 0) {
+ fprintf(stderr, "failed to map output image: %d\n", err);
+ return 1;
+ }
+
+ memset(ptr, 0xff, output->size);
+ drm_tegra_bo_unmap(output->bo);
+
+ printf("output: %ux%u\n", output->width, output->height);
+ vic_image_dump(output, stdout);
+
+ err = drm_tegra_job_new(channel, &job);
+ if (err < 0) {
+ fprintf(stderr, "failed to create job: %s\n", strerror(-err));
+ return 1;
+ }
+
+ err = drm_tegra_job_get_pushbuf(job, &pushbuf);
+ if (err < 0) {
+ fprintf(stderr, "failed to create push buffer: %s\n", strerror(-err));
+ return 1;
+ }
+
+ err = drm_tegra_pushbuf_begin(pushbuf, 32, &pb);
+ if (err < 0) {
+ fprintf(stderr, "failed to prepare push buffer: %s\n", strerror(-err));
+ return 1;
+ }
+
+ err = vic_clear(vic, output, 1023, 0, 0, 1023);
+ if (err < 0) {
+ fprintf(stderr, "failed to clear surface: %s\n", strerror(-err));
+ return err;
+ }
+
+ err = vic->ops->execute(vic, pushbuf, &pb, output, NULL, 0);
+ if (err < 0) {
+ fprintf(stderr, "failed to execute operation: %s\n", strerror(-err));
+ return 1;
+ }
+
+ err = drm_tegra_pushbuf_sync_cond(pushbuf, &pb, vic->syncpt,
+ DRM_TEGRA_SYNC_COND_OP_DONE);
+ if (err < 0) {
+ fprintf(stderr, "failed to push syncpoint: %s\n", strerror(-err));
+ return 1;
+ }
+
+ err = drm_tegra_pushbuf_end(pushbuf, pb);
+ if (err < 0) {
+ fprintf(stderr, "failed to update push buffer: %s\n", strerror(-err));
+ return 1;
+ }
+
+ err = drm_tegra_job_submit(job, NULL);
+ if (err < 0) {
+ fprintf(stderr, "failed to submit job: %s\n", strerror(-err));
+ return 1;
+ }
+
+ err = drm_tegra_job_wait(job, 1000000000);
+ if (err < 0) {
+ fprintf(stderr, "failed to wait for job: %s\n", strerror(-err));
+ return 1;
+ }
+
+ printf("output: %ux%u\n", output->width, output->height);
+ vic_image_dump(output, stdout);
+
+ drm_tegra_job_free(job);
+ vic_image_free(output);
+ vic_free(vic);
+ drm_tegra_channel_close(channel);
+ drm_tegra_close(drm);
+ close(fd);
+
+ return 0;
+}
|
|
[-]
[+]
|
Added |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/tegra/vic-flip.c
^
|
| @@ -0,0 +1,333 @@
+/*
+ * Copyright © 2018 NVIDIA Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <errno.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <string.h>
+#include <unistd.h>
+
+#include "tegra.h"
+
+#include "host1x.h"
+#include "vic.h"
+
+/* clear output image to red */
+static int clear(struct vic *vic, struct drm_tegra_channel *channel,
+ struct vic_image *output)
+{
+ struct drm_tegra_pushbuf *pushbuf;
+ struct drm_tegra_job *job;
+ uint32_t *ptr;
+ int err;
+
+ err = drm_tegra_job_new(channel, &job);
+ if (err < 0) {
+ fprintf(stderr, "failed to create job: %s\n", strerror(-err));
+ return 1;
+ }
+
+ err = drm_tegra_job_get_pushbuf(job, &pushbuf);
+ if (err < 0) {
+ fprintf(stderr, "failed to create push buffer: %s\n", strerror(-err));
+ return 1;
+ }
+
+ err = drm_tegra_pushbuf_begin(pushbuf, 32, &ptr);
+ if (err < 0) {
+ fprintf(stderr, "failed to prepare push buffer: %s\n", strerror(-err));
+ return err;
+ }
+
+ err = vic_clear(vic, output, 1023, 0, 0, 1023);
+ if (err < 0) {
+ fprintf(stderr, "failed to clear surface: %s\n", strerror(-err));
+ return err;
+ }
+
+ err = vic->ops->execute(vic, pushbuf, &ptr, output, NULL, 0);
+ if (err < 0) {
+ fprintf(stderr, "failed to execute operation: %s\n", strerror(-err));
+ return err;
+ }
+
+ err = drm_tegra_pushbuf_sync_cond(pushbuf, &ptr, vic->syncpt,
+ DRM_TEGRA_SYNC_COND_OP_DONE);
+ if (err < 0) {
+ fprintf(stderr, "failed to push syncpoint: %s\n", strerror(-err));
+ return err;
+ }
+
+ err = drm_tegra_pushbuf_end(pushbuf, ptr);
+ if (err < 0) {
+ fprintf(stderr, "failed to update push buffer: %s\n", strerror(-err));
+ return err;
+ }
+
+ err = drm_tegra_job_submit(job, NULL);
+ if (err < 0) {
+ fprintf(stderr, "failed to submit job: %s\n", strerror(-err));
+ return err;
+ }
+
+ err = drm_tegra_job_wait(job, 1000000000);
+ if (err < 0) {
+ fprintf(stderr, "failed to wait for job: %s\n", strerror(-err));
+ return err;
+ }
+
+ drm_tegra_job_free(job);
+
+ return 0;
+}
+
+/* fill bottom half of image to blue */
+static int fill(struct vic *vic, struct drm_tegra_channel *channel,
+ struct vic_image *output)
+{
+ struct drm_tegra_pushbuf *pushbuf;
+ struct drm_tegra_job *job;
+ uint32_t *ptr;
+ int err;
+
+ err = drm_tegra_job_new(channel, &job);
+ if (err < 0) {
+ fprintf(stderr, "failed to create job: %s\n", strerror(-err));
+ return 1;
+ }
+
+ err = drm_tegra_job_get_pushbuf(job, &pushbuf);
+ if (err < 0) {
+ fprintf(stderr, "failed to create push buffer: %s\n", strerror(-err));
+ return 1;
+ }
+
+ err = drm_tegra_pushbuf_begin(pushbuf, 32, &ptr);
+ if (err < 0) {
+ fprintf(stderr, "failed to prepare push buffer: %s\n", strerror(-err));
+ return err;
+ }
+
+ err = vic->ops->fill(vic, output, 0, output->height / 2, output->width - 1,
+ output->height - 1, 0, 0, 1023, 1023);
+ if (err < 0) {
+ fprintf(stderr, "failed ot fill surface: %s\n", strerror(-err));
+ return err;
+ }
+
+ err = vic->ops->execute(vic, pushbuf, &ptr, output, NULL, 0);
+ if (err < 0) {
+ fprintf(stderr, "failed to execute operation: %s\n", strerror(-err));
+ return err;
+ }
+
+ err = drm_tegra_pushbuf_sync_cond(pushbuf, &ptr, vic->syncpt,
+ DRM_TEGRA_SYNC_COND_OP_DONE);
+ if (err < 0) {
+ fprintf(stderr, "failed to push syncpoint: %s\n", strerror(-err));
+ return err;
+ }
+
+ err = drm_tegra_pushbuf_end(pushbuf, ptr);
+ if (err < 0) {
+ fprintf(stderr, "failed to update push buffer: %s\n", strerror(-err));
+ return err;
+ }
+
+ err = drm_tegra_job_submit(job, NULL);
+ if (err < 0) {
+ fprintf(stderr, "failed to submit job: %s\n", strerror(-err));
+ return err;
+ }
+
+ err = drm_tegra_job_wait(job, 1000000000);
+ if (err < 0) {
+ fprintf(stderr, "failed to wait for job: %s\n", strerror(-err));
+ return err;
+ }
+
+ drm_tegra_job_free(job);
+
+ return 0;
+}
+
+/* flip image vertically */
+static int flip(struct vic *vic, struct drm_tegra_channel *channel,
+ struct vic_image *output, struct vic_image *input)
+{
+ struct drm_tegra_pushbuf *pushbuf;
+ struct drm_tegra_job *job;
+ uint32_t *ptr;
+ int err;
+
+ err = drm_tegra_job_new(channel, &job);
+ if (err < 0) {
+ fprintf(stderr, "failed to create job: %s\n", strerror(-err));
+ return 1;
+ }
+
+ err = drm_tegra_job_get_pushbuf(job, &pushbuf);
+ if (err < 0) {
+ fprintf(stderr, "failed to create push buffer: %s\n", strerror(-err));
+ return 1;
+ }
+
+ err = drm_tegra_pushbuf_begin(pushbuf, 32, &ptr);
+ if (err < 0) {
+ fprintf(stderr, "failed to prepare push buffer: %s\n", strerror(-err));
+ return err;
+ }
+
|
|
[-]
[+]
|
Added |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/tegra/vic.c
^
|
| @@ -0,0 +1,184 @@
+/*
+ * Copyright © 2018 NVIDIA Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <errno.h>
+#include <stdio.h> /* XXX remove */
+#include <stdlib.h>
+
+#include "util_math.h"
+
+#include "tegra.h"
+#include "host1x.h"
+#include "vic.h"
+
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
+
+const struct vic_format_info *vic_format_get_info(unsigned int format)
+{
+ static const struct vic_format_info formats[] = {
+ { .format = VIC_PIXEL_FORMAT_A8R8G8B8, .cpp = 4 },
+ };
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(formats); i++) {
+ if (formats[i].format == format)
+ return &formats[i];
+ }
+
+ return 0;
+}
+
+int vic_image_new(struct vic *vic, unsigned int width, unsigned int height,
+ unsigned int format, unsigned int kind, uint32_t flags,
+ struct vic_image **imagep)
+{
+ const struct vic_format_info *info = vic_format_get_info(format);
+ struct vic_image *image;
+ int err;
+
+ if (!info)
+ return -EINVAL;
+
+ image = calloc(1, sizeof(*image));
+ if (!image)
+ return -ENOMEM;
+
+ if (kind == VIC_BLK_KIND_PITCH)
+ image->align = 256;
+ else
+ image->align = 256; /* XXX */
+
+ image->width = width;
+ image->stride = ALIGN(width, image->align);
+ image->pitch = image->stride * info->cpp;
+ image->height = height;
+ image->format = format;
+ image->kind = kind;
+
+ image->size = image->pitch * image->height;
+
+ printf("image: %ux%u align: %zu stride: %u pitch: %u size: %zu\n",
+ image->width, image->height, image->align, image->stride,
+ image->pitch, image->size);
+
+ err = drm_tegra_bo_new(vic->drm, 0, image->size, &image->bo);
+ if (err < 0) {
+ free(image);
+ return err;
+ }
+
+ err = drm_tegra_channel_map(vic->channel, image->bo, flags, &image->map);
+ if (err < 0) {
+ drm_tegra_bo_unref(image->bo);
+ free(image);
+ return err;
+ }
+
+ *imagep = image;
+ return 0;
+}
+
+void vic_image_free(struct vic_image *image)
+{
+ if (image) {
+ drm_tegra_channel_unmap(image->map);
+ drm_tegra_bo_unref(image->bo);
+ free(image);
+ }
+}
+
+void vic_image_dump(struct vic_image *image, FILE *fp)
+{
+ unsigned int i, j;
+ void *ptr;
+ int err;
+
+ err = drm_tegra_bo_map(image->bo, &ptr);
+ if (err < 0)
+ return;
+
+ for (j = 0; j < image->height; j++) {
+ uint32_t *pixels = (uint32_t *)((unsigned long)ptr + j * image->pitch);
+
+ printf(" ");
+
+ for (i = 0; i < image->width; i++)
+ printf(" %08x", pixels[i]);
+
+ printf("\n");
+ }
+
+ drm_tegra_bo_unmap(image->bo);
+}
+
+/* from vic30.c */
+int vic30_new(struct drm_tegra *drm, struct drm_tegra_channel *channel,
+ struct vic **vicp);
+
+/* from vic40.c */
+int vic40_new(struct drm_tegra *drm, struct drm_tegra_channel *channel,
+ struct vic **vicp);
+
+/* from vic41.c */
+int vic41_new(struct drm_tegra *drm, struct drm_tegra_channel *channel,
+ struct vic **vicp);
+
+/* from vic42.c */
+int vic42_new(struct drm_tegra *drm, struct drm_tegra_channel *channel,
+ struct vic **vicp);
+
+int vic_new(struct drm_tegra *drm, struct drm_tegra_channel *channel,
+ struct vic **vicp)
+{
+ unsigned int version;
+
+ version = drm_tegra_channel_get_version(channel);
+
+ switch (version) {
+ case 0x40:
+ return vic30_new(drm, channel, vicp);
+
+ case 0x21:
+ return vic40_new(drm, channel, vicp);
+
+ case 0x18:
+ return vic41_new(drm, channel, vicp);
+
+ case 0x19:
+ return vic42_new(drm, channel, vicp);
+ }
+
+ return -ENOTSUP;
+}
+
+void vic_free(struct vic *vic)
+{
+ if (vic)
+ vic->ops->free(vic);
+}
+
+int vic_clear(struct vic *vic, struct vic_image *output, unsigned int alpha,
+ unsigned int red, unsigned int green, unsigned int blue)
+{
+ return vic->ops->fill(vic, output, 0, 0, output->width - 1,
+ output->height - 1, alpha, red, green, blue);
+}
|
|
[-]
[+]
|
Added |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/tegra/vic.h
^
|
| @@ -0,0 +1,181 @@
+/*
+ * Copyright © 2018 NVIDIA Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef VIC_H
+#define VIC_H
+
+#include <stdio.h>
+
+#include "host1x.h"
+
+#define DXVAHD_FRAME_FORMAT_PROGRESSIVE 0
+#define DXVAHD_FRAME_FORMAT_INTERLACED_TOP_FIELD_FIRST 1
+#define DXVAHD_FRAME_FORMAT_INTERLACED_BOTTOM_FIELD_FIRST 2
+#define DXVAHD_FRAME_FORMAT_TOP_FIELD 3
+#define DXVAHD_FRAME_FORMAT_BOTTOM_FIELD 4
+#define DXVAHD_FRAME_FORMAT_SUBPIC_PROGRESSIVE 5
+#define DXVAHD_FRAME_FORMAT_SUBPIC_INTERLACED_TOP_FIELD_FIRST 6
+#define DXVAHD_FRAME_FORMAT_SUBPIC_INTERLACED_BOTTOM_FIELD_FIRST 7
+#define DXVAHD_FRAME_FORMAT_SUBPIC_TOP_FIELD 8
+#define DXVAHD_FRAME_FORMAT_SUBPIC_BOTTOM_FIELD 9
+#define DXVAHD_FRAME_FORMAT_TOP_FIELD_CHROMA_BOTTOM 10
+#define DXVAHD_FRAME_FORMAT_BOTTOM_FIELD_CHROMA_TOP 11
+#define DXVAHD_FRAME_FORMAT_SUBPIC_TOP_FIELD_CHROMA_BOTTOM 12
+#define DXVAHD_FRAME_FORMAT_SUBPIC_BOTTOM_FIELD_CHROMA_TOP 13
+
+#define DXVAHD_ALPHA_FILL_MODE_OPAQUE 0
+#define DXVAHD_ALPHA_FILL_MODE_BACKGROUND 1
+#define DXVAHD_ALPHA_FILL_MODE_DESTINATION 2
+#define DXVAHD_ALPHA_FILL_MODE_SOURCE_STREAM 3
+#define DXVAHD_ALPHA_FILL_MODE_COMPOSITED 4
+#define DXVAHD_ALPHA_FILL_MODE_SOURCE_ALPHA 5
+
+#define VIC_BLEND_SRCFACTC_K1 0
+#define VIC_BLEND_SRCFACTC_K1_TIMES_DST 1
+#define VIC_BLEND_SRCFACTC_NEG_K1_TIMES_DST 2
+#define VIC_BLEND_SRCFACTC_K1_TIMES_SRC 3
+#define VIC_BLEND_SRCFACTC_ZERO 4
+
+#define VIC_BLEND_DSTFACTC_K1 0
+#define VIC_BLEND_DSTFACTC_K2 1
+#define VIC_BLEND_DSTFACTC_K1_TIMES_DST 2
+#define VIC_BLEND_DSTFACTC_NEG_K1_TIMES_DST 3
+#define VIC_BLEND_DSTFACTC_NEG_K1_TIMES_SRC 4
+#define VIC_BLEND_DSTFACTC_ZERO 5
+#define VIC_BLEND_DSTFACTC_ONE 6
+
+#define VIC_BLEND_SRCFACTA_K1 0
+#define VIC_BLEND_SRCFACTA_K2 1
+#define VIC_BLEND_SRCFACTA_NEG_K1_TIMES_DST 2
+#define VIC_BLEND_SRCFACTA_ZERO 3
+
+#define VIC_BLEND_DSTFACTA_K2 0
+#define VIC_BLEND_DSTFACTA_NEG_K1_TIMES_SRC 1
+#define VIC_BLEND_DSTFACTA_ZERO 2
+#define VIC_BLEND_DSTFACTA_ONE 3
+
+#define VIC_BLK_KIND_PITCH 0
+#define VIC_BLK_KIND_GENERIC_16Bx2 1
+
+#define VIC_PIXEL_FORMAT_L8 1
+#define VIC_PIXEL_FORMAT_R8 4
+#define VIC_PIXEL_FORMAT_A8R8G8B8 32
+#define VIC_PIXEL_FORMAT_R8G8B8A8 34
+#define VIC_PIXEL_FORMAT_Y8_U8V8_N420 67
+#define VIC_PIXEL_FORMAT_Y8_V8U8_N420 68
+
+#define VIC_CACHE_WIDTH_16Bx16 0 /* BL16Bx2 */
+#define VIC_CACHE_WIDTH_32Bx8 1 /* BL16Bx2 */
+#define VIC_CACHE_WIDTH_64Bx4 2 /* BL16Bx2, PL */
+#define VIC_CACHE_WIDTH_128Bx2 3 /* BL16Bx2, PL */
+#define VIC_CACHE_WIDTH_256Bx1 4 /* PL */
+
+struct vic_format_info {
+ unsigned int format;
+ unsigned int cpp;
+};
+
+
+#define VIC_UCLASS_INCR_SYNCPT 0x00
+#define VIC_UCLASS_METHOD_OFFSET 0x10
+#define VIC_UCLASS_METHOD_DATA 0x11
+
+static inline void VIC_PUSH_METHOD(struct drm_tegra_pushbuf *pushbuf,
+ uint32_t **ptrp, uint32_t method,
+ uint32_t value)
+{
+ *(*ptrp)++ = HOST1X_OPCODE_INCR(VIC_UCLASS_METHOD_OFFSET, 2);
+ *(*ptrp)++ = method >> 2;
+ *(*ptrp)++ = value;
+}
+
+static inline void VIC_PUSH_BUFFER(struct drm_tegra_pushbuf *pushbuf,
+ uint32_t **ptrp, uint32_t method,
+ struct drm_tegra_mapping *map,
+ unsigned long offset, unsigned long flags)
+{
+ *(*ptrp)++ = HOST1X_OPCODE_INCR(VIC_UCLASS_METHOD_OFFSET, 2);
+ *(*ptrp)++ = method >> 2;
+
+ drm_tegra_pushbuf_relocate(pushbuf, ptrp, map, offset, 8, flags);
+}
+
+struct vic_image;
+struct vic;
+
+struct vic_ops {
+ int (*fill)(struct vic *vic, struct vic_image *output,
+ unsigned int left, unsigned int top,
+ unsigned int right, unsigned int bottom,
+ unsigned int alpha, unsigned red,
+ unsigned int green, unsigned int blue);
+ int (*blit)(struct vic *vic, struct vic_image *output,
+ struct vic_image *input);
+ int (*flip)(struct vic *vic, struct vic_image *output,
+ struct vic_image *input);
+ int (*execute)(struct vic *vic,
+ struct drm_tegra_pushbuf *pushbuf,
+ uint32_t **ptrp,
+ struct vic_image *output,
+ struct vic_image **inputs,
+ unsigned int num_inputs);
+ void (*free)(struct vic *vic);
+};
+
+struct vic {
+ struct drm_tegra *drm;
+ struct drm_tegra_channel *channel;
+ struct drm_tegra_syncpoint *syncpt;
+ const struct vic_ops *ops;
+ unsigned int version;
+};
+
+int vic_new(struct drm_tegra *drm, struct drm_tegra_channel *channel,
+ struct vic **vicp);
+void vic_free(struct vic *vic);
+
+int vic_clear(struct vic *vic, struct vic_image *output, unsigned int alpha,
+ unsigned int red, unsigned int green, unsigned int blue);
+
+struct vic_image {
+ struct drm_tegra_bo *bo;
+ struct drm_tegra_mapping *map;
+ unsigned int width;
+ unsigned int stride;
+ unsigned int pitch;
+ unsigned int height;
+ unsigned int format;
+ unsigned int kind;
+
+ size_t align;
+ size_t size;
+};
+
+const struct vic_format_info *vic_format_get_info(unsigned int format);
+
+int vic_image_new(struct vic *vic, unsigned int width, unsigned int height,
+ unsigned int format, unsigned int kind, uint32_t flags,
+ struct vic_image **imagep);
+void vic_image_free(struct vic_image *image);
+void vic_image_dump(struct vic_image *image, FILE *fp);
+
+#endif
|
|
[-]
[+]
|
Added |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/tegra/vic30.c
^
|
| @@ -0,0 +1,458 @@
+/*
+ * Copyright © 2018 NVIDIA Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <errno.h>
+#include <string.h>
+
+#include "private.h"
+#include "tegra.h"
+#include "vic.h"
+#include "vic30.h"
+
+struct vic30 {
+ struct vic base;
+
+ struct {
+ struct drm_tegra_mapping *map;
+ struct drm_tegra_bo *bo;
+ } config;
+
+ struct {
+ struct drm_tegra_mapping *map;
+ struct drm_tegra_bo *bo;
+ } filter;
+
+ struct {
+ struct drm_tegra_mapping *map;
+ struct drm_tegra_bo *bo;
+ } hist;
+};
+
+static int vic30_fill(struct vic *v, struct vic_image *output,
+ unsigned int left, unsigned int top,
+ unsigned int right, unsigned int bottom,
+ unsigned int alpha, unsigned int red,
+ unsigned int green, unsigned int blue)
+{
+ struct vic30 *vic = container_of(v, struct vic30, base);
+ ConfigStruct *c;
+ int err;
+
+ err = drm_tegra_bo_map(vic->config.bo, (void **)&c);
+ if (err < 0) {
+ fprintf(stderr, "failed to map configuration structure: %s\n",
+ strerror(-err));
+ return err;
+ }
+
+ memset(c, 0, sizeof(*c));
+
+ c->surfaceList0Struct.TargetRectLeft = left;
+ c->surfaceList0Struct.TargetRectTop = top;
+ c->surfaceList0Struct.TargetRectRight = right;
+ c->surfaceList0Struct.TargetRectBottom = bottom;
+
+ c->blending0Struct.PixelFormat = output->format;
+ c->blending0Struct.BackgroundAlpha = alpha;
+ c->blending0Struct.BackgroundR = red;
+ c->blending0Struct.BackgroundG = green;
+ c->blending0Struct.BackgroundB = blue;
+ c->blending0Struct.LumaWidth = output->stride - 1;
+ c->blending0Struct.LumaHeight = output->height - 1;
+ c->blending0Struct.ChromaWidth = 16383;
+ c->blending0Struct.ChromaWidth = 16383;
+ c->blending0Struct.TargetRectLeft = left;
+ c->blending0Struct.TargetRectTop = top;
+ c->blending0Struct.TargetRectRight = right;
+ c->blending0Struct.TargetRectBottom = bottom;
+ c->blending0Struct.SurfaceWidth = output->width - 1;
+ c->blending0Struct.SurfaceHeight = output->height - 1;
+ c->blending0Struct.BlkKind = output->kind;
+ c->blending0Struct.BlkHeight = 0;
+
+ c->fetchControl0Struct.TargetRectLeft = left;
+ c->fetchControl0Struct.TargetRectTop = top;
+ c->fetchControl0Struct.TargetRectRight = right;
+ c->fetchControl0Struct.TargetRectBottom = bottom;
+
+ drm_tegra_bo_unmap(vic->config.bo);
+
+ return 0;
+}
+
+static int vic30_blit(struct vic *v, struct vic_image *output,
+ struct vic_image *input)
+{
+ struct vic30 *vic = container_of(v, struct vic30, base);
+ ColorConversionLumaAlphaStruct *ccla;
+ ColorConversionMatrixStruct *ccm;
+ ColorConversionClampStruct *ccc;
+ SurfaceListSurfaceStruct *s;
+ BlendingSurfaceStruct *b;
+ SurfaceCache0Struct *sc;
+ ConfigStruct *c;
+ int err;
+
+ err = drm_tegra_bo_map(vic->config.bo, (void **)&c);
+ if (err < 0) {
+ fprintf(stderr, "failed to map configuration structure: %s\n",
+ strerror(-err));
+ return err;
+ }
+
+ memset(c, 0, sizeof(*c));
+
+ c->surfaceList0Struct.TargetRectLeft = 0;
+ c->surfaceList0Struct.TargetRectTop = 0;
+ c->surfaceList0Struct.TargetRectRight = output->width - 1;
+ c->surfaceList0Struct.TargetRectBottom = output->height - 1;
+
+ c->blending0Struct.PixelFormat = output->format;
+ c->blending0Struct.BackgroundAlpha = 0;
+ c->blending0Struct.BackgroundR = 0;
+ c->blending0Struct.BackgroundG = 0;
+ c->blending0Struct.BackgroundB = 0;
+ c->blending0Struct.LumaWidth = output->stride - 1;
+ c->blending0Struct.LumaHeight = output->height - 1;
+ c->blending0Struct.ChromaWidth = 16383;
+ c->blending0Struct.ChromaWidth = 16383;
+ c->blending0Struct.TargetRectLeft = 0;
+ c->blending0Struct.TargetRectTop = 0;
+ c->blending0Struct.TargetRectRight = output->width - 1;
+ c->blending0Struct.TargetRectBottom = output->height - 1;
+ c->blending0Struct.SurfaceWidth = output->width - 1;
+ c->blending0Struct.SurfaceHeight = output->height - 1;
+ c->blending0Struct.BlkKind = output->kind;
+ c->blending0Struct.BlkHeight = 0;
+
+ c->fetchControl0Struct.TargetRectLeft = 0;
+ c->fetchControl0Struct.TargetRectTop = 0;
+ c->fetchControl0Struct.TargetRectRight = output->width - 1;
+ c->fetchControl0Struct.TargetRectBottom = output->height - 1;
+
+ /* setup fetch parameters for slot 0 */
+ c->fetchControl0Struct.Enable0 = 0x1;
+ c->fetchControl0Struct.Iir0 = 0x300;
+
+ /* setup cache parameters for slot 0 */
+ sc = &c->surfaceCache0Struct;
+ sc->PixelFormat0 = input->format;
+
+ /* setup surface configuration for slot 0 */
+ s = &c->surfaceListSurfaceStruct[0];
+ s->Enable = 1;
+ s->FrameFormat = DXVAHD_FRAME_FORMAT_PROGRESSIVE;
+ s->PixelFormat = input->format;
+ s->SurfaceWidth = input->width - 1;
+ s->SurfaceHeight = input->height - 1;
+ s->LumaWidth = input->stride - 1;
+ s->LumaHeight = input->height - 1;
+ s->ChromaWidth = 16383;
+ s->ChromaHeight = 16383;
+ s->CacheWidth = VIC_CACHE_WIDTH_256Bx1; //VIC_CACHE_WIDTH_16Bx16;
+ s->BlkKind = input->kind;
+ s->BlkHeight = 0;
+ s->DestRectLeft = 0;
+ s->DestRectTop = 0;
+ s->DestRectRight = output->width - 1;
+ s->DestRectBottom = output->height - 1;
+ s->SourceRectLeft = 0 << 16;
+ s->SourceRectTop = 0 << 16;
+ s->SourceRectRight = (input->width - 1) << 16;
+ s->SourceRectBottom = (input->height - 1) << 16;
+
+ /* setup color conversion for slot 0 */
+ ccla = &c->colorConversionLumaAlphaStruct[0];
+ ccla->PlanarAlpha = 1023;
+ ccla->ConstantAlpha = 0;
+
+ ccm = &c->colorConversionMatrixStruct[0];
+ ccm->c00 = 1023;
+ ccm->c11 = 1023;
+ ccm->c22 = 1023;
+
+ ccc = &c->colorConversionClampStruct[0];
+ ccc->low = 0;
+ ccc->high = 1023;
+
+ /* setup blending for slot 0 */
+ b = &c->blendingSurfaceStruct[0];
+ b->AlphaK1 = 1023;
|
|
[-]
[+]
|
Added |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/tegra/vic30.h
^
|
| @@ -0,0 +1,439 @@
+/*
+ * Copyright © 2018 NVIDIA Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef VIC30_H
+#define VIC30_H
+
+#include <stdint.h>
+
+#define NVA0B6_VIDEO_COMPOSITOR_SET_APPLICATION_ID 0x200
+#define NVA0B6_VIDEO_COMPOSITOR_EXECUTE 0x300
+#define NVA0B6_VIDEO_COMPOSITOR_EXECUTE_AWAKEN (1 << 8)
+#define NVA0B6_VIDEO_COMPOSITOR_SET_SURFACE0_SLOT0_LUMA_OFFSET 0x400
+#define NVA0B6_VIDEO_COMPOSITOR_SET_SURFACE0_SLOT0_CHROMA_U_OFFSET 0x404
+#define NVA0B6_VIDEO_COMPOSITOR_SET_SURFACE0_SLOT0_CHROMA_V_OFFSET 0x408
+#define NVA0B6_VIDEO_COMPOSITOR_SET_CONTROL_PARAMS 0x700
+#define NVA0B6_VIDEO_COMPOSITOR_SET_CONFIG_STRUCT_OFFSET 0x720
+#define NVA0B6_VIDEO_COMPOSITOR_SET_PALETTE_OFFSET 0x724
+#define NVA0B6_VIDEO_COMPOSITOR_SET_HIST_OFFSET 0x728
+#define NVA0B6_VIDEO_COMPOSITOR_SET_OUTPUT_SURFACE_LUMA_OFFSET 0x730
+#define NVA0B6_VIDEO_COMPOSITOR_SET_OUTPUT_SURFACE_CHROMA_U_OFFSET 0x734
+#define NVA0B6_VIDEO_COMPOSITOR_SET_OUTPUT_SURFACE_CHROMA_V_OFFSET 0x738
+
+#define VIC_PIXEL_FORMAT_L8 1
+#define VIC_PIXEL_FORMAT_R8 4
+#define VIC_PIXEL_FORMAT_A8R8G8B8 32
+#define VIC_PIXEL_FORMAT_R8G8B8A8 34
+#define VIC_PIXEL_FORMAT_Y8_U8V8_N420 67
+#define VIC_PIXEL_FORMAT_Y8_V8U8_N420 68
+
+#define VIC_BLK_KIND_PITCH 0
+#define VIC_BLK_KIND_GENERIC_16Bx2 1
+
+typedef struct {
+ uint64_t DeNoise0 : 1; /* 0 */
+ uint64_t CadenceDetect0 : 1; /* 1 */
+ uint64_t MotionMap0 : 1; /* 2 */
+ uint64_t MedianFilter0 : 1; /* 3 */
+ uint64_t DeNoise1 : 1; /* 4 */
+ uint64_t CadenceDetect1 : 1; /* 5 */
+ uint64_t MotionMap1 : 1; /* 6 */
+ uint64_t MedianFilter1 : 1; /* 7 */
+ uint64_t DeNoise2 : 1; /* 8 */
+ uint64_t CadenceDetect2 : 1; /* 9 */
+ uint64_t MotionMap2 : 1; /* 10 */
+ uint64_t MedianFilter2 : 1; /* 11 */
+ uint64_t DeNoise3 : 1; /* 12 */
+ uint64_t CadenceDetect3 : 1; /* 13 */
+ uint64_t MotionMap3 : 1; /* 14 */
+ uint64_t MedianFilter3 : 1; /* 15 */
+ uint64_t DeNoise4 : 1; /* 16 */
+ uint64_t CadenceDetect4 : 1; /* 17 */
+ uint64_t MotionMap4 : 1; /* 18 */
+ uint64_t MedianFilter4 : 1; /* 19 */
+ uint64_t IsEven0 : 1; /* 20 */
+ uint64_t IsEven1 : 1; /* 21 */
+ uint64_t IsEven2 : 1; /* 22 */
+ uint64_t IsEven3 : 1; /* 23 */
+ uint64_t IsEven4 : 1; /* 24 */
+ uint64_t MMapCombine0 : 1; /* 25 */
+ uint64_t MMapCombine1 : 1; /* 26 */
+ uint64_t MMapCombine2 : 1; /* 27 */
+ uint64_t MMapCombine3 : 1; /* 28 */
+ uint64_t MMapCombine4 : 1; /* 29 */
+ uint64_t reserved0 : 2; /* 31..30 */
+ uint64_t PixelFormat0 : 7; /* 38..32 */
+ uint64_t reserved1 : 1; /* 39 */
+ uint64_t PixelFormat1 : 7; /* 46..40 */
+ uint64_t reserved2 : 1; /* 47 */
+ uint64_t PixelFormat2 : 7; /* 54..48 */
+ uint64_t reserved3 : 1; /* 55 */
+ uint64_t PixelFormat3 : 7; /* 62..56 */
+ uint64_t reserved4 : 1; /* 63 */
+ uint64_t PixelFormat4 : 7; /* 70..64 */
+ uint64_t reserved5 : 1; /* 71 */
+ uint64_t reserved6 : 24; /* 95..72 */
+ uint64_t PPMotion0 : 1; /* 96 */
+ uint64_t PPMotion1 : 1; /* 97 */
+ uint64_t PPMotion2 : 1; /* 98 */
+ uint64_t PPMotion3 : 1; /* 99 */
+ uint64_t PPMotion4 : 1; /* 100 */
+ uint64_t reserved7 : 3; /* 103..101 */
+ uint64_t ChromaEven0 : 1; /* 104 */
+ uint64_t ChromaEven1 : 1; /* 105 */
+ uint64_t ChromaEven2 : 1; /* 106 */
+ uint64_t ChromaEven3 : 1; /* 107 */
+ uint64_t ChromaEven4 : 1; /* 108 */
+ uint64_t reserved8 : 3; /* 111..109 */
+ uint64_t AdvancedDenoise0 : 1; /* 112 */
+ uint64_t AdvancedDenoise1 : 1; /* 113 */
+ uint64_t AdvancedDenoise2 : 1; /* 114 */
+ uint64_t AdvancedDenoise3 : 1; /* 115 */
+ uint64_t AdvancedDenoise4 : 1; /* 116 */
+ uint64_t reserved9 : 3; /* 119..117 */
+ uint64_t reserved10 : 8; /* 127..120 */
+} SurfaceCache0Struct;
+
+typedef struct {
+ uint64_t ClearRectMask0 : 8; /* 7..0 */
+ uint64_t ClearRectMask1 : 8; /* 15..8 */
+ uint64_t ClearRectMask2 : 8; /* 23..16 */
+ uint64_t ClearRectMask3 : 8; /* 31..24 */
+ uint64_t ClearRectMask4 : 8; /* 39..32 */
+ uint64_t reserved0 : 22; /* 61..40 */
+ uint64_t OutputFlipX : 1; /* 62 */
+ uint64_t OutputFlipY : 1; /* 63 */
+ uint64_t TargetRectLeft : 14; /* 77..64 */
+ uint64_t reserved1 : 2; /* 79..78 */
+ uint64_t TargetRectRight : 14; /* 93..80 */
+ uint64_t reserved2 : 2; /* 95..94 */
+ uint64_t TargetRectTop : 14; /* 109..96 */
+ uint64_t reserved3 : 2; /* 111..110 */
+ uint64_t TargetRectBottom : 14; /* 125..112 */
+ uint64_t reserved4 : 2; /* 127..126 */
+} SurfaceList0Struct;
+
+typedef struct {
+ uint64_t ClearRect0Left : 14; /* 13..0 */
+ uint64_t reserved0 : 2; /* 15..14 */
+ uint64_t ClearRect0Right : 14; /* 29..16 */
+ uint64_t reserved1 : 2; /* 31..30 */
+ uint64_t ClearRect0Top : 14; /* 45..32 */
+ uint64_t reserved2 : 2; /* 47..46 */
+ uint64_t ClearRect0Bottom : 14; /* 61..48 */
+ uint64_t reserved3 : 2; /* 63..62 */
+ uint64_t ClearRect1Left : 14; /* 77..64 */
+ uint64_t reserved4 : 2; /* 79..78 */
+ uint64_t ClearRect1Right : 14; /* 93..80 */
+ uint64_t reserved5 : 2; /* 95..94 */
+ uint64_t ClearRect1Top : 14; /* 109..96 */
+ uint64_t reserved6 : 2; /* 111..110 */
+ uint64_t ClearRect1Bottom : 14; /* 125..112 */
+ uint64_t reserved7 : 2; /* 127..126 */
+} SurfaceListClearRectStruct;
+
+typedef struct {
+ uint64_t Enable : 1; /* 0 */
+ uint64_t FrameFormat : 4; /* 4..1 */
+ uint64_t PixelFormat : 7; /* 11..5 */
+ uint64_t reserved0 : 2; /* 13..12 */
+ uint64_t ChromaLocHoriz : 2; /* 15..14 */
+ uint64_t ChromaLocVert : 2; /* 17..16 */
+ uint64_t Panoramic : 12; /* 29..18 */
+ uint64_t reserved1 : 4; /* 33..30 */
+ uint64_t SurfaceWidth : 14; /* 47..34 */
+ uint64_t reserved2 : 1; /* 48 */
+ uint64_t SurfaceHeight : 14; /* 62..49 */
+ uint64_t reserved3 : 1; /* 63 */
+ uint64_t LumaWidth : 14; /* 77..64 */
+ uint64_t reserved4 : 1; /* 78 */
+ uint64_t LumaHeight : 14; /* 92..79 */
+ uint64_t reserved5 : 1; /* 93 */
+ uint64_t ChromaWidth : 14; /* 107..94 */
+ uint64_t reserved6 : 1; /* 108 */
+ uint64_t ChromaHeight : 14; /* 122..109 */
+ uint64_t reserved7 : 1; /* 123 */
+ uint64_t CacheWidth : 3; /* 126..124 */
+ uint64_t reserved8 : 1; /* 127 */
+ /* 128 */
+ uint64_t FilterLengthY : 2; /* 1..0 */
+ uint64_t FilterLengthX : 2; /* 3..2 */
+ uint64_t DetailFltClamp : 6; /* 9..4 */
+ uint64_t reserved9 : 2; /* 11..10 */
+ uint64_t LightLevel : 4; /* 15..12 */
+ uint64_t reserved10 : 4; /* 19..16 */
+ uint64_t reserved11 : 8; /* 27..20 */
+ uint64_t reserved12 : 32; /* 59..28 */
+ uint64_t BlkKind : 4; /* 63..60 */
+ uint64_t DestRectLeft : 14; /* 77..64 */
+ uint64_t reserved13 : 1; /* 78 */
+ uint64_t DestRectRight : 14; /* 92..79 */
+ uint64_t reserved14 : 1; /* 93 */
+ uint64_t DestRectTop : 14; /* 107..94 */
+ uint64_t reserved15 : 1; /* 108 */
+ uint64_t DestRectBottom : 14; /* 122..109 */
+ uint64_t reserved16 : 1; /* 123 */
+ uint64_t BlkHeight : 4; /* 127..124 */
+ /* 256 */
+ uint64_t SourceRectLeft : 30; /* 29..0 */
+ uint64_t reserved17 : 2; /* 31..30 */
+ uint64_t SourceRectRight : 30; /* 61..32 */
|
|
[-]
[+]
|
Added |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/tegra/vic40.c
^
|
| @@ -0,0 +1,338 @@
+/*
+ * Copyright © 2018 NVIDIA Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <errno.h>
+#include <string.h>
+
+#include "private.h"
+#include "tegra.h"
+#include "vic.h"
+#include "vic40.h"
+
+struct vic40 {
+ struct vic base;
+
+ struct {
+ struct drm_tegra_mapping *map;
+ struct drm_tegra_bo *bo;
+ } config;
+
+ struct {
+ struct drm_tegra_mapping *map;
+ struct drm_tegra_bo *bo;
+ } filter;
+};
+
+static int vic40_fill(struct vic *v, struct vic_image *output,
+ unsigned int left, unsigned int top,
+ unsigned int right, unsigned int bottom,
+ unsigned int alpha, unsigned int red,
+ unsigned int green, unsigned int blue)
+{
+ struct vic40 *vic = container_of(v, struct vic40, base);
+ ConfigStruct *c;
+ int err;
+
+ err = drm_tegra_bo_map(vic->config.bo, (void **)&c);
+ if (err < 0) {
+ fprintf(stderr, "failed to map configuration structure: %s\n",
+ strerror(-err));
+ return err;
+ }
+
+ memset(c, 0, sizeof(*c));
+
+ c->outputConfig.TargetRectTop = top;
+ c->outputConfig.TargetRectLeft = left;
+ c->outputConfig.TargetRectRight = right;
+ c->outputConfig.TargetRectBottom = bottom;
+ c->outputConfig.BackgroundAlpha = alpha;
+ c->outputConfig.BackgroundR = red;
+ c->outputConfig.BackgroundG = green;
+ c->outputConfig.BackgroundB = blue;
+
+ c->outputSurfaceConfig.OutPixelFormat = output->format;
+ c->outputSurfaceConfig.OutBlkKind = output->kind;
+ c->outputSurfaceConfig.OutBlkHeight = 0;
+ c->outputSurfaceConfig.OutSurfaceWidth = output->width - 1;
+ c->outputSurfaceConfig.OutSurfaceHeight = output->height - 1;
+ c->outputSurfaceConfig.OutLumaWidth = output->stride - 1;
+ c->outputSurfaceConfig.OutLumaHeight = output->height - 1;
+ c->outputSurfaceConfig.OutChromaWidth = 16383;
+ c->outputSurfaceConfig.OutChromaHeight = 16383;
+
+ drm_tegra_bo_unmap(vic->config.bo);
+
+ return 0;
+}
+
+static int vic40_blit(struct vic *v, struct vic_image *output,
+ struct vic_image *input)
+{
+ struct vic40 *vic = container_of(v, struct vic40, base);
+ SlotSurfaceConfig *surface;
+ SlotConfig *slot;
+ ConfigStruct *c;
+ int err;
+
+ err = drm_tegra_bo_map(vic->config.bo, (void **)&c);
+ if (err < 0) {
+ fprintf(stderr, "failed to map configuration structure: %s\n",
+ strerror(-err));
+ return err;
+ }
+
+ memset(c, 0, sizeof(*c));
+
+ c->outputConfig.TargetRectTop = 0;
+ c->outputConfig.TargetRectLeft = 0;
+ c->outputConfig.TargetRectRight = output->width - 1;
+ c->outputConfig.TargetRectBottom = output->height - 1;
+ c->outputConfig.BackgroundAlpha = 1023;
+ c->outputConfig.BackgroundR = 1023;
+ c->outputConfig.BackgroundG = 1023;
+ c->outputConfig.BackgroundB = 1023;
+
+ c->outputSurfaceConfig.OutPixelFormat = output->format;
+ c->outputSurfaceConfig.OutBlkKind = output->kind;
+ c->outputSurfaceConfig.OutBlkHeight = 0;
+ c->outputSurfaceConfig.OutSurfaceWidth = output->width - 1;
+ c->outputSurfaceConfig.OutSurfaceHeight = output->height - 1;
+ c->outputSurfaceConfig.OutLumaWidth = output->stride - 1;
+ c->outputSurfaceConfig.OutLumaHeight = output->height - 1;
+ c->outputSurfaceConfig.OutChromaWidth = 16383;
+ c->outputSurfaceConfig.OutChromaHeight = 16383;
+
+ slot = &c->slotStruct[0].slotConfig;
+ slot->SlotEnable = 1;
+ slot->CurrentFieldEnable = 1;
+ slot->PlanarAlpha = 1023;
+ slot->ConstantAlpha = 1;
+ slot->SourceRectLeft = 0 << 16;
+ slot->SourceRectRight = (input->width - 1) << 16;
+ slot->SourceRectTop = 0 << 16;
+ slot->SourceRectBottom = (input->height - 1) << 16;
+ slot->DestRectLeft = 0;
+ slot->DestRectRight = output->width - 1;
+ slot->DestRectTop = 0;
+ slot->DestRectBottom = output->height - 1;
+ slot->SoftClampHigh = 1023;
+
+ surface = &c->slotStruct[0].slotSurfaceConfig;
+ surface->SlotPixelFormat = input->format;
+ surface->SlotBlkKind = input->kind;
+ surface->SlotBlkHeight = 0; /* XXX */
+ surface->SlotCacheWidth = VIC_CACHE_WIDTH_64Bx4; /* XXX */
+ surface->SlotSurfaceWidth = input->width - 1;
+ surface->SlotSurfaceHeight = input->height - 1;
+ surface->SlotLumaWidth = input->stride - 1;
+ surface->SlotLumaHeight = input->height - 1;
+ surface->SlotChromaWidth = 16383;
+ surface->SlotChromaHeight = 16383;
+
+ drm_tegra_bo_unmap(vic->config.bo);
+
+ return 0;
+}
+
+static int vic40_flip(struct vic *v, struct vic_image *output,
+ struct vic_image *input)
+{
+ struct vic40 *vic = container_of(v, struct vic40, base);
+ SlotSurfaceConfig *surface;
+ SlotConfig *slot;
+ ConfigStruct *c;
+ int err;
+
+ err = drm_tegra_bo_map(vic->config.bo, (void **)&c);
+ if (err < 0) {
+ fprintf(stderr, "failed to map configuration structure: %s\n",
+ strerror(-err));
+ return err;
+ }
+
+ memset(c, 0, sizeof(*c));
+
+ c->outputConfig.TargetRectTop = 0;
+ c->outputConfig.TargetRectLeft = 0;
+ c->outputConfig.TargetRectRight = output->width - 1;
+ c->outputConfig.TargetRectBottom = output->height - 1;
+ c->outputConfig.BackgroundAlpha = 1023;
+ c->outputConfig.BackgroundR = 1023;
+ c->outputConfig.BackgroundG = 1023;
+ c->outputConfig.BackgroundB = 1023;
+ c->outputConfig.OutputFlipY = 1;
+
+ c->outputSurfaceConfig.OutPixelFormat = output->format;
+ c->outputSurfaceConfig.OutBlkKind = output->kind;
+ c->outputSurfaceConfig.OutBlkHeight = 0;
+ c->outputSurfaceConfig.OutSurfaceWidth = output->width - 1;
+ c->outputSurfaceConfig.OutSurfaceHeight = output->height - 1;
+ c->outputSurfaceConfig.OutLumaWidth = output->stride - 1;
+ c->outputSurfaceConfig.OutLumaHeight = output->height - 1;
+ c->outputSurfaceConfig.OutChromaWidth = 16383;
+ c->outputSurfaceConfig.OutChromaHeight = 16383;
+
+ slot = &c->slotStruct[0].slotConfig;
+ slot->SlotEnable = 1;
+ slot->CurrentFieldEnable = 1;
+ slot->PlanarAlpha = 1023;
+ slot->ConstantAlpha = 1;
|
|
[-]
[+]
|
Added |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/tegra/vic40.h
^
|
| @@ -0,0 +1,285 @@
+/*
+ * Copyright © 2016-2018 NVIDIA Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef VIC40_H
+#define VIC40_H
+
+#include <stdint.h>
+
+#define NVB0B6_VIDEO_COMPOSITOR_SET_APPLICATION_ID 0x00000200
+#define NVB0B6_VIDEO_COMPOSITOR_EXECUTE 0x00000300
+#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE0_SLOT0_LUMA_OFFSET 0x00000400
+#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE0_SLOT0_CHROMA_U_OFFSET 0x00000404
+#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE0_SLOT0_CHROMA_V_OFFSET 0x00000408
+#define NVB0B6_VIDEO_COMPOSITOR_SET_CONTROL_PARAMS 0x00000704
+#define NVB0B6_VIDEO_COMPOSITOR_SET_CONFIG_STRUCT_OFFSET 0x00000708
+#define NVB0B6_VIDEO_COMPOSITOR_SET_HIST_OFFSET 0x00000714
+#define NVB0B6_VIDEO_COMPOSITOR_SET_OUTPUT_SURFACE_LUMA_OFFSET 0x00000720
+
+typedef struct {
+ uint64_t SlotEnable : 1; /* 0 */
+ uint64_t DeNoise : 1; /* 1 */
+ uint64_t AdvancedDenoise : 1; /* 2 */
+ uint64_t CadenceDetect : 1; /* 3 */
+ uint64_t MotionMap : 1; /* 4 */
+ uint64_t MMapCombine : 1; /* 5 */
+ uint64_t IsEven : 1; /* 6 */
+ uint64_t ChromaEven : 1; /* 7 */
+ uint64_t CurrentFieldEnable : 1; /* 8 */
+ uint64_t PrevFieldEnable : 1; /* 9 */
+ uint64_t NextFieldEnable : 1; /* 10 */
+ uint64_t NextNrFieldEnable : 1; /* 11 */
+ uint64_t CurMotionFieldEnable : 1; /* 12 */
+ uint64_t PrevMotionFieldEnable : 1; /* 13 */
+ uint64_t PpMotionFieldEnable : 1; /* 14 */
+ uint64_t CombMotionFieldEnable : 1; /* 15 */
+ uint64_t FrameFormat : 4; /* 19..16 */
+ uint64_t FilterLengthY : 2; /* 21..20 */
+ uint64_t FilterLengthX : 2; /* 23..22 */
+ uint64_t Panoramic : 12; /* 35..24 */
+ uint64_t reserved1 : 22; /* 57..36 */
+ uint64_t DetailFltClamp : 6; /* 63..58 */
+ uint64_t FilterNoise : 10; /* 73..64 */
+ uint64_t FilterDetail : 10; /* 83..74 */
+ uint64_t ChromaNoise : 10; /* 93..84 */
+ uint64_t ChromaDetail : 10; /* 103..94 */
+ uint64_t DeinterlaceMode : 4; /* 107..104 */
+ uint64_t MotionAccumWeight : 3; /* 110..108 */
+ uint64_t NoiseIir : 11; /* 121..111 */
+ uint64_t LightLevel : 4; /* 125..122 */
+ uint64_t reserved4 : 2; /* 127..126 */
+ /* 128 */
+ uint64_t SoftClampLow : 10; /* 9..0 */
+ uint64_t SoftClampHigh : 10; /* 19..10 */
+ uint64_t reserved5 : 3; /* 22..20 */
+ uint64_t reserved6 : 9; /* 31..23 */
+ uint64_t PlanarAlpha : 10; /* 41..32 */
+ uint64_t ConstantAlpha : 1; /* 42 */
+ uint64_t StereoInterleave : 3; /* 45..43 */
+ uint64_t ClipEnabled : 1; /* 46 */
+ uint64_t ClearRectMask : 8; /* 54..47 */
+ uint64_t DegammaMode : 2; /* 56..55 */
+ uint64_t reserved7 : 1; /* 57 */
+ uint64_t DecompressEnable : 1; /* 58 */
+ uint64_t reserved9 : 5; /* 63..59 */
+ uint64_t DecompressCtbCount : 8; /* 71..64 */
+ uint64_t DecompressZbcColor : 32; /* 103..72 */
+ uint64_t reserved12 : 24; /* 127..104 */
+ /* 256 */
+ uint64_t SourceRectLeft : 30; /* 29..0 */
+ uint64_t reserved14 : 2; /* 31..30 */
+ uint64_t SourceRectRight : 30; /* 61..32 */
+ uint64_t reserved15 : 2; /* 63..62 */
+ uint64_t SourceRectTop : 30; /* 93..64 */
+ uint64_t reserved16 : 2; /* 95..94 */
+ uint64_t SourceRectBottom : 30; /* 125..96 */
+ uint64_t reserved17 : 2; /* 127..126 */
+ /* 384 */
+ uint64_t DestRectLeft : 14; /* 13..0 */
+ uint64_t reserved18 : 2; /* 15..14 */
+ uint64_t DestRectRight : 14; /* 29..16 */
+ uint64_t reserved19 : 2; /* 31..30 */
+ uint64_t DestRectTop : 14; /* 45..32 */
+ uint64_t reserved20 : 2; /* 47..46 */
+ uint64_t DestRectBottom : 14; /* 61..48 */
+ uint64_t reserved21 : 2; /* 63..62 */
+ uint64_t reserved22 : 32; /* 95..64 */
+ uint64_t reserved23 : 32; /* 127..96 */
+} SlotConfig;
+
+typedef struct {
+ uint64_t SlotPixelFormat : 7; /* 6..0 */
+ uint64_t SlotChromaLocHoriz : 2; /* 8..7 */
+ uint64_t SlotChromaLocVert : 2; /* 10..9 */
+ uint64_t SlotBlkKind : 4; /* 14..11 */
+ uint64_t SlotBlkHeight : 4; /* 18..15 */
+ uint64_t SlotCacheWidth : 3; /* 21..19 */
+ uint64_t reserved0 : 10; /* 31..22 */
+ uint64_t SlotSurfaceWidth : 14; /* 45..32 */
+ uint64_t SlotSurfaceHeight : 14; /* 59..46 */
+ uint64_t reserved1 : 4; /* 63..60 */
+ uint64_t SlotLumaWidth : 14; /* 77..64 */
+ uint64_t SlotLumaHeight : 14; /* 91..78 */
+ uint64_t reserved2 : 4; /* 95..92 */
+ uint64_t SlotChromaWidth : 14; /* 109..96 */
+ uint64_t SlotChromaHeight : 14; /* 123..110 */
+ uint64_t reserved3 : 4; /* 127..124 */
+} SlotSurfaceConfig;
+
+typedef struct {
+ uint64_t luma_coeff0 : 20; /* 19..0 */
+ uint64_t luma_coeff1 : 20; /* 39..20 */
+ uint64_t luma_coeff2 : 20; /* 59..40 */
+ uint64_t luma_r_shift : 4; /* 63..60 */
+ uint64_t luma_coeff3 : 20; /* 83..64 */
+ uint64_t LumaKeyLower : 10; /* 93..84 */
+ uint64_t LumaKeyUpper : 10; /* 103..94 */
+ uint64_t LumaKeyEnabled : 1; /* 104 */
+ uint64_t reserved0 : 2; /* 106..105 */
+ uint64_t reserved1 : 21; /* 127..107 */
+} LumaKeyStruct;
+
+typedef struct {
+ uint64_t matrix_coeff00 : 20; /* 19..0 */
+ uint64_t matrix_coeff10 : 20; /* 39..20 */
+ uint64_t matrix_coeff20 : 20; /* 59..40 */
+ uint64_t matrix_r_shift : 4; /* 63..60 */
+ uint64_t matrix_coeff01 : 20; /* 83..64 */
+ uint64_t matrix_coeff11 : 20; /* 103..84 */
+ uint64_t matrix_coeff21 : 20; /* 123..104 */
+ uint64_t reserved0 : 3; /* 126..124 */
+ uint64_t matrix_enable : 1; /* 127 */
+ /* 128 */
+ uint64_t matrix_coeff02 : 20; /* 19..0 */
+ uint64_t matrix_coeff12 : 20; /* 39..20 */
+ uint64_t matrix_coeff22 : 20; /* 59..40 */
+ uint64_t reserved1 : 4; /* 63..60 */
+ uint64_t matrix_coeff03 : 20; /* 83..64 */
+ uint64_t matrix_coeff13 : 20; /* 103..84 */
+ uint64_t matrix_coeff23 : 20; /* 123..104 */
+ uint64_t reserved2 : 4; /* 127..124 */
+} MatrixStruct;
+
+typedef struct {
+ uint64_t ClearRect0Left : 14; /* 13..0 */
+ uint64_t reserved0 : 2; /* 15..14 */
+ uint64_t ClearRect0Right : 14; /* 29..16 */
+ uint64_t reserved1 : 2; /* 31..30 */
+ uint64_t ClearRect0Top : 14; /* 45..32 */
+ uint64_t reserved2 : 2; /* 47..46 */
+ uint64_t ClearRect0Bottom : 14; /* 61..48 */
+ uint64_t reserved3 : 2; /* 63..62 */
+ uint64_t ClearRect1Left : 14; /* 77..64 */
+ uint64_t reserved4 : 2; /* 79..78 */
+ uint64_t ClearRect1Right : 14; /* 93..80 */
+ uint64_t reserved5 : 2; /* 95..94 */
+ uint64_t ClearRect1Top : 14; /* 109..96 */
+ uint64_t reserved6 : 2; /* 111..110 */
+ uint64_t ClearRect1Bottom : 14; /* 125..112 */
+ uint64_t reserved7 : 2; /* 127..126 */
+} ClearRectStruct;
+
+typedef struct {
+ uint64_t AlphaK1 : 10; /* 9..0 */
+ uint64_t reserved0 : 6; /* 15..10 */
+ uint64_t AlphaK2 : 10; /* 25..16 */
+ uint64_t reserved1 : 6; /* 31..26 */
+ uint64_t SrcFactCMatchSelect : 3; /* 34..32 */
+ uint64_t reserved2 : 1; /* 35 */
+ uint64_t DstFactCMatchSelect : 3; /* 38..36 */
+ uint64_t reserved3 : 1; /* 39 */
+ uint64_t SrcFactAMatchSelect : 3; /* 42..40 */
+ uint64_t reserved4 : 1; /* 43 */
+ uint64_t DstFactAMatchSelect : 3; /* 46..44 */
+ uint64_t reserved5 : 1; /* 47 */
+ uint64_t reserved6 : 4; /* 51..48 */
+ uint64_t reserved7 : 4; /* 55..52 */
+ uint64_t reserved8 : 4; /* 59..56 */
+ uint64_t reserved9 : 4; /* 63..60 */
+ uint64_t reserved10 : 2; /* 65..64 */
+ uint64_t OverrideR : 10; /* 75..66 */
|
|
[-]
[+]
|
Added |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/tegra/vic41.c
^
|
| @@ -0,0 +1,342 @@
+/*
+ * Copyright © 2018 NVIDIA Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <errno.h>
+#include <string.h>
+
+#include "private.h"
+#include "tegra.h"
+#include "vic.h"
+#include "vic41.h"
+
+struct vic41 {
+ struct vic base;
+
+ struct {
+ struct drm_tegra_mapping *map;
+ struct drm_tegra_bo *bo;
+ } config;
+
+ struct {
+ struct drm_tegra_mapping *map;
+ struct drm_tegra_bo *bo;
+ } filter;
+};
+
+static int vic41_fill(struct vic *v, struct vic_image *output,
+ unsigned int left, unsigned int top,
+ unsigned int right, unsigned int bottom,
+ unsigned int alpha, unsigned int red,
+ unsigned int green, unsigned int blue)
+{
+ struct vic41 *vic = container_of(v, struct vic41, base);
+ ConfigStruct *c;
+ int err;
+
+ err = drm_tegra_bo_map(vic->config.bo, (void **)&c);
+ if (err < 0) {
+ fprintf(stderr, "failed to map configuration structure: %s\n",
+ strerror(-err));
+ return err;
+ }
+
+ memset(c, 0, sizeof(*c));
+
+ c->outputConfig.TargetRectTop = top;
+ c->outputConfig.TargetRectLeft = left;
+ c->outputConfig.TargetRectRight = right;
+ c->outputConfig.TargetRectBottom = bottom;
+ c->outputConfig.BackgroundAlpha = alpha;
+ c->outputConfig.BackgroundR = red;
+ c->outputConfig.BackgroundG = green;
+ c->outputConfig.BackgroundB = blue;
+
+ c->outputSurfaceConfig.OutPixelFormat = output->format;
+ c->outputSurfaceConfig.OutBlkKind = output->kind;
+ c->outputSurfaceConfig.OutBlkHeight = 0;
+ c->outputSurfaceConfig.OutSurfaceWidth = output->width - 1;
+ c->outputSurfaceConfig.OutSurfaceHeight = output->height - 1;
+ c->outputSurfaceConfig.OutLumaWidth = output->stride - 1;
+ c->outputSurfaceConfig.OutLumaHeight = output->height - 1;
+ c->outputSurfaceConfig.OutChromaWidth = 16383;
+ c->outputSurfaceConfig.OutChromaHeight = 16383;
+
+ drm_tegra_bo_unmap(vic->config.bo);
+
+ return 0;
+}
+
+static int vic41_blit(struct vic *v, struct vic_image *output,
+ struct vic_image *input)
+{
+ struct vic41 *vic = container_of(v, struct vic41, base);
+ SlotSurfaceConfig *surface;
+ SlotConfig *slot;
+ ConfigStruct *c;
+ int err;
+
+ err = drm_tegra_bo_map(vic->config.bo, (void **)&c);
+ if (err < 0) {
+ fprintf(stderr, "failed to map configuration structure: %s\n",
+ strerror(-err));
+ return err;
+ }
+
+ memset(c, 0, sizeof(*c));
+
+ c->outputConfig.TargetRectTop = 0;
+ c->outputConfig.TargetRectLeft = 0;
+ c->outputConfig.TargetRectRight = output->width - 1;
+ c->outputConfig.TargetRectBottom = output->height - 1;
+ c->outputConfig.BackgroundAlpha = 255;
+ c->outputConfig.BackgroundR = 1023;
+ c->outputConfig.BackgroundG = 1023;
+ c->outputConfig.BackgroundB = 1023;
+
+ c->outputSurfaceConfig.OutPixelFormat = output->format;
+ c->outputSurfaceConfig.OutBlkKind = output->kind;
+ c->outputSurfaceConfig.OutBlkHeight = 0;
+ c->outputSurfaceConfig.OutSurfaceWidth = output->width - 1;
+ c->outputSurfaceConfig.OutSurfaceHeight = output->height - 1;
+ c->outputSurfaceConfig.OutLumaWidth = output->stride - 1;
+ c->outputSurfaceConfig.OutLumaHeight = output->height - 1;
+ c->outputSurfaceConfig.OutChromaWidth = 16383;
+ c->outputSurfaceConfig.OutChromaHeight = 16383;
+
+ slot = &c->slotStruct[0].slotConfig;
+ slot->SlotEnable = 1;
+ slot->CurrentFieldEnable = 1;
+ slot->PlanarAlpha = 255;
+ slot->ConstantAlpha = 1;
+ slot->SourceRectLeft = 0 << 16;
+ slot->SourceRectRight = (input->width - 1) << 16;
+ slot->SourceRectTop = 0 << 16;
+ slot->SourceRectBottom = (input->height - 1) << 16;
+ slot->DestRectLeft = 0;
+ slot->DestRectRight = output->width - 1;
+ slot->DestRectTop = 0;
+ slot->DestRectBottom = output->height - 1;
+ slot->SoftClampHigh = 1023;
+
+ surface = &c->slotStruct[0].slotSurfaceConfig;
+ surface->SlotPixelFormat = input->format;
+ surface->SlotBlkKind = input->kind;
+ surface->SlotBlkHeight = 0; /* XXX */
+ surface->SlotCacheWidth = VIC_CACHE_WIDTH_64Bx4; /* XXX */
+ surface->SlotSurfaceWidth = input->width - 1;
+ surface->SlotSurfaceHeight = input->height - 1;
+ surface->SlotLumaWidth = input->stride - 1;
+ surface->SlotLumaHeight = input->height - 1;
+ surface->SlotChromaWidth = 16383;
+ surface->SlotChromaHeight = 16383;
+
+ drm_tegra_bo_unmap(vic->config.bo);
+
+ return 0;
+}
+
+static int vic41_flip(struct vic *v, struct vic_image *output,
+ struct vic_image *input)
+{
+ struct vic41 *vic = container_of(v, struct vic41, base);
+ SlotSurfaceConfig *surface;
+ SlotConfig *slot;
+ ConfigStruct *c;
+ int err;
+
+ err = drm_tegra_bo_map(vic->config.bo, (void **)&c);
+ if (err < 0) {
+ fprintf(stderr, "failed to map configuration structure: %s\n",
+ strerror(-err));
+ return err;
+ }
+
+ memset(c, 0, sizeof(*c));
+
+ c->outputConfig.TargetRectTop = 0;
+ c->outputConfig.TargetRectLeft = 0;
+ c->outputConfig.TargetRectRight = output->width - 1;
+ c->outputConfig.TargetRectBottom = output->height - 1;
+ c->outputConfig.BackgroundAlpha = 255;
+ c->outputConfig.BackgroundR = 1023;
+ c->outputConfig.BackgroundG = 1023;
+ c->outputConfig.BackgroundB = 1023;
+ c->outputConfig.OutputFlipY = 1;
+
+ c->outputSurfaceConfig.OutPixelFormat = output->format;
+ c->outputSurfaceConfig.OutBlkKind = output->kind;
+ c->outputSurfaceConfig.OutBlkHeight = 0;
+ c->outputSurfaceConfig.OutSurfaceWidth = output->width - 1;
+ c->outputSurfaceConfig.OutSurfaceHeight = output->height - 1;
+ c->outputSurfaceConfig.OutLumaWidth = output->stride - 1;
+ c->outputSurfaceConfig.OutLumaHeight = output->height - 1;
+ c->outputSurfaceConfig.OutChromaWidth = 16383;
+ c->outputSurfaceConfig.OutChromaHeight = 16383;
+
+ slot = &c->slotStruct[0].slotConfig;
+ slot->SlotEnable = 1;
+ slot->CurrentFieldEnable = 1;
+ slot->PlanarAlpha = 255;
+ slot->ConstantAlpha = 1;
|
|
[-]
[+]
|
Added |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/tegra/vic41.h
^
|
| @@ -0,0 +1,372 @@
+/*
+ * Copyright © 2018 NVIDIA Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef VIC41_H
+#define VIC41_H
+
+#include <stdint.h>
+
+#define NVB1B6_VIDEO_COMPOSITOR_SET_APPLICATION_ID 0x00000200
+#define NVB1B6_VIDEO_COMPOSITOR_EXECUTE 0x00000300
+#define NVB1B6_VIDEO_COMPOSITOR_SET_PICTURE_INDEX 0x00000700
+#define NVB1B6_VIDEO_COMPOSITOR_SET_CONTROL_PARAMS 0x00000704
+#define NVB1B6_VIDEO_COMPOSITOR_SET_CONFIG_STRUCT_OFFSET 0x00000708
+#define NVB1B6_VIDEO_COMPOSITOR_SET_FILTER_STRUCT_OFFSET 0x0000070c
+#define NVB1B6_VIDEO_COMPOSITOR_SET_HIST_OFFSET 0x00000714
+#define NVB1B6_VIDEO_COMPOSITOR_SET_OUTPUT_SURFACE_LUMA_OFFSET 0x00000720
+#define NVB1B6_VIDEO_COMPOSITOR_SET_HISTORY_BUFFER_OFFSET(slot) (0x00000780 + (slot) * 4)
+#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE0_LUMA_OFFSET(slot) (0x00001200 + (slot) * 0x00000060)
+#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE0_CHROMA_U_OFFSET(slot) (0x00001204 + (slot) * 0x00000060)
+#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE0_CHROMA_V_OFFSET(slot) (0x00001208 + (slot) * 0x00000060)
+#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE1_LUMA_OFFSET(slot) (0x0000120c + (slot) * 0x00000060)
+#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE1_CHROMA_U_OFFSET(slot) (0x00001210 + (slot) * 0x00000060)
+#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE1_CHROMA_V_OFFSET(slot) (0x00001214 + (slot) * 0x00000060)
+#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE2_LUMA_OFFSET(slot) (0x00001218 + (slot) * 0x00000060)
+#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE2_CHROMA_U_OFFSET(slot) (0x0000121c + (slot) * 0x00000060)
+#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE2_CHROMA_V_OFFSET(slot) (0x00001220 + (slot) * 0x00000060)
+#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE3_LUMA_OFFSET(slot) (0x00001224 + (slot) * 0x00000060)
+#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE3_CHROMA_U_OFFSET(slot) (0x00001228 + (slot) * 0x00000060)
+#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE3_CHROMA_V_OFFSET(slot) (0x0000122c + (slot) * 0x00000060)
+#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE4_LUMA_OFFSET(slot) (0x00001230 + (slot) * 0x00000060)
+#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE4_CHROMA_U_OFFSET(slot) (0x00001234 + (slot) * 0x00000060)
+#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE4_CHROMA_V_OFFSET(slot) (0x00001238 + (slot) * 0x00000060)
+#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE5_LUMA_OFFSET(slot) (0x0000123c + (slot) * 0x00000060)
+#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE5_CHROMA_U_OFFSET(slot) (0x00001240 + (slot) * 0x00000060)
+#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE5_CHROMA_V_OFFSET(slot) (0x00001244 + (slot) * 0x00000060)
+#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE6_LUMA_OFFSET(slot) (0x00001248 + (slot) * 0x00000060)
+#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE6_CHROMA_U_OFFSET(slot) (0x0000124c + (slot) * 0x00000060)
+#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE6_CHROMA_V_OFFSET(slot) (0x00001250 + (slot) * 0x00000060)
+#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE7_LUMA_OFFSET(slot) (0x00001254 + (slot) * 0x00000060)
+#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE7_CHROMA_U_OFFSET(slot) (0x00001258 + (slot) * 0x00000060)
+#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE7_CHROMA_V_OFFSET(slot) (0x0000125c + (slot) * 0x00000060)
+
+typedef struct {
+ uint64_t SlotEnable : 1; /* 0 */
+ uint64_t DeNoise : 1; /* 1 */
+ uint64_t AdvancedDenoise : 1; /* 2 */
+ uint64_t CadenceDetect : 1; /* 3 */
+ uint64_t MotionMap : 1; /* 4 */
+ uint64_t MMapCombine : 1; /* 5 */
+ uint64_t IsEven : 1; /* 6 */
+ uint64_t ChromaEven : 1; /* 7 */
+ uint64_t CurrentFieldEnable : 1; /* 8 */
+ uint64_t PrevFieldEnable : 1; /* 9 */
+ uint64_t NextFieldEnable : 1; /* 10 */
+ uint64_t NextNrFieldEnable : 1; /* 11 */
+ uint64_t CurMotionFieldEnable : 1; /* 12 */
+ uint64_t PrevMotionFieldEnable : 1; /* 13 */
+ uint64_t PpMotionFieldEnable : 1; /* 14 */
+ uint64_t CombMotionFieldEnable : 1; /* 15 */
+ uint64_t FrameFormat : 4; /* 19..16 */
+ uint64_t FilterLengthY : 2; /* 21..20 */
+ uint64_t FilterLengthX : 2; /* 23..22 */
+ uint64_t Panoramic : 12; /* 35..24 */
+ uint64_t ChromaUpLengthY : 2; /* 37..36 */
+ uint64_t ChromaUpLengthX : 2; /* 39..38 */
+ uint64_t reserved1 : 18; /* 57..40 */
+ uint64_t DetailFltClamp : 6; /* 63..58 */
+ uint64_t FilterNoise : 10; /* 73..64 */
+ uint64_t FilterDetail : 10; /* 83..74 */
+ uint64_t ChromaNoise : 10; /* 93..84 */
+ uint64_t ChromaDetail : 10; /* 103..94 */
+ uint64_t DeinterlaceMode : 4; /* 107..104 */
+ uint64_t MotionAccumWeight : 3; /* 110..108 */
+ uint64_t NoiseIir : 11; /* 121..111 */
+ uint64_t LightLevel : 4; /* 125..122 */
+ uint64_t reserved4 : 2; /* 127..126 */
+ /* 128 */
+ uint64_t SoftClampLow : 10; /* 9..0 */
+ uint64_t SoftClampHigh : 10; /* 19..10 */
+ uint64_t reserved5 : 12; /* 31..20 */
+ uint64_t reserved6 : 2; /* 33..32 */
+ uint64_t PlanarAlpha : 8; /* 41..34 */
+ uint64_t ConstantAlpha : 1; /* 42 */
+ uint64_t StereoInterleave : 3; /* 45..43 */
+ uint64_t ClipEnabled : 1; /* 46 */
+ uint64_t ClearRectMask : 8; /* 54..47 */
+ uint64_t DegammaMode : 2; /* 56..55 */
+ uint64_t reserved7 : 1; /* 57 */
+ uint64_t DecompressEnable : 1; /* 58 */
+ uint64_t DecompressKind : 4; /* 62..59 */
+ uint64_t reserved9 : 1; /* 63 */
+ uint64_t DecompressCtbCount : 8; /* 71..64 */
+ uint64_t DecompressZbcColor : 32; /* 103..72 */
+ uint64_t reserved12 : 24; /* 127..104 */
+ /* 256 */
+ uint64_t SourceRectLeft : 30; /* 29..0 */
+ uint64_t reserved14 : 2; /* 31..30 */
+ uint64_t SourceRectRight : 30; /* 61..32 */
+ uint64_t reserved15 : 2; /* 63..62 */
+ uint64_t SourceRectTop : 30; /* 93..64 */
+ uint64_t reserved16 : 2; /* 95..94 */
+ uint64_t SourceRectBottom : 30; /* 125..96 */
+ uint64_t reserved17 : 2; /* 127..126 */
+ /* 384 */
+ uint64_t DestRectLeft : 14; /* 13..0 */
+ uint64_t reserved18 : 2; /* 15..14 */
+ uint64_t DestRectRight : 14; /* 29..16 */
+ uint64_t reserved19 : 2; /* 31..30 */
+ uint64_t DestRectTop : 14; /* 45..32 */
+ uint64_t reserved20 : 2; /* 47..46 */
+ uint64_t DestRectBottom : 14; /* 61..48 */
+ uint64_t reserved21 : 2; /* 63..62 */
+ uint64_t reserved22 : 32; /* 95..64 */
+ uint64_t reserved23 : 32; /* 127..96 */
+} SlotConfig;
+
+typedef struct {
+ uint64_t SlotPixelFormat : 7; /* 6..0 */
+ uint64_t SlotChromaLocHoriz : 2; /* 8..7 */
+ uint64_t SlotChromaLocVert : 2; /* 10..9 */
+ uint64_t SlotBlkKind : 4; /* 14..11 */
+ uint64_t SlotBlkHeight : 4; /* 18..15 */
+ uint64_t SlotCacheWidth : 3; /* 21..19 */
+ uint64_t reserved0 : 10; /* 31..22 */
+ uint64_t SlotSurfaceWidth : 14; /* 45..32 */
+ uint64_t SlotSurfaceHeight : 14; /* 59..46 */
+ uint64_t reserved1 : 4; /* 63..60 */
+ uint64_t SlotLumaWidth : 14; /* 77..64 */
+ uint64_t SlotLumaHeight : 14; /* 91..78 */
+ uint64_t reserved2 : 4; /* 95..92 */
+ uint64_t SlotChromaWidth : 14; /* 109..96 */
+ uint64_t SlotChromaHeight : 14; /* 123..110 */
+ uint64_t reserved3 : 4; /* 127..124 */
+} SlotSurfaceConfig;
+
+typedef struct {
+ uint64_t luma_coeff0 : 20; /* 19..0 */
+ uint64_t luma_coeff1 : 20; /* 39..20 */
+ uint64_t luma_coeff2 : 20; /* 59..40 */
+ uint64_t luma_r_shift : 4; /* 63..60 */
+ uint64_t luma_coeff3 : 20; /* 83..64 */
+ uint64_t LumaKeyLower : 10; /* 93..84 */
+ uint64_t LumaKeyUpper : 10; /* 103..94 */
+ uint64_t LumaKeyEnabled : 1; /* 104 */
+ uint64_t reserved0 : 2; /* 106..105 */
+ uint64_t reserved1 : 21; /* 127..107 */
+} LumaKeyStruct;
+
+typedef struct {
+ uint64_t matrix_coeff00 : 20; /* 19..0 */
+ uint64_t matrix_coeff10 : 20; /* 39..20 */
+ uint64_t matrix_coeff20 : 20; /* 59..40 */
+ uint64_t matrix_r_shift : 4; /* 63..60 */
+ uint64_t matrix_coeff01 : 20; /* 83..64 */
+ uint64_t matrix_coeff11 : 20; /* 103..84 */
+ uint64_t matrix_coeff21 : 20; /* 123..104 */
+ uint64_t reserved0 : 3; /* 126..124 */
+ uint64_t matrix_enable : 1; /* 127 */
+ /* 128 */
+ uint64_t matrix_coeff02 : 20; /* 19..0 */
+ uint64_t matrix_coeff12 : 20; /* 39..20 */
+ uint64_t matrix_coeff22 : 20; /* 59..40 */
+ uint64_t reserved1 : 4; /* 63..60 */
+ uint64_t matrix_coeff03 : 20; /* 83..64 */
+ uint64_t matrix_coeff13 : 20; /* 103..84 */
+ uint64_t matrix_coeff23 : 20; /* 123..104 */
+ uint64_t reserved2 : 4; /* 127..124 */
+} MatrixStruct;
+
+typedef struct {
+ uint64_t ClearRect0Left : 14; /* 13..0 */
+ uint64_t reserved0 : 2; /* 15..14 */
+ uint64_t ClearRect0Right : 14; /* 29..16 */
+ uint64_t reserved1 : 2; /* 31..30 */
+ uint64_t ClearRect0Top : 14; /* 45..32 */
+ uint64_t reserved2 : 2; /* 47..46 */
+ uint64_t ClearRect0Bottom : 14; /* 61..48 */
+ uint64_t reserved3 : 2; /* 63..62 */
+ uint64_t ClearRect1Left : 14; /* 77..64 */
+ uint64_t reserved4 : 2; /* 79..78 */
|
|
[-]
[+]
|
Added |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/tegra/vic42.c
^
|
| @@ -0,0 +1,342 @@
+/*
+ * Copyright © 2018 NVIDIA Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <errno.h>
+#include <string.h>
+
+#include "private.h"
+#include "tegra.h"
+#include "vic.h"
+#include "vic42.h"
+
+struct vic42 {
+ struct vic base;
+
+ struct {
+ struct drm_tegra_mapping *map;
+ struct drm_tegra_bo *bo;
+ } config;
+
+ struct {
+ struct drm_tegra_mapping *map;
+ struct drm_tegra_bo *bo;
+ } filter;
+};
+
+static int vic42_fill(struct vic *v, struct vic_image *output,
+ unsigned int left, unsigned int top,
+ unsigned int right, unsigned int bottom,
+ unsigned int alpha, unsigned int red,
+ unsigned int green, unsigned int blue)
+{
+ struct vic42 *vic = container_of(v, struct vic42, base);
+ ConfigStruct *c;
+ int err;
+
+ err = drm_tegra_bo_map(vic->config.bo, (void **)&c);
+ if (err < 0) {
+ fprintf(stderr, "failed to map configuration structure: %s\n",
+ strerror(-err));
+ return err;
+ }
+
+ memset(c, 0, sizeof(*c));
+
+ c->outputConfig.TargetRectTop = top;
+ c->outputConfig.TargetRectLeft = left;
+ c->outputConfig.TargetRectRight = right;
+ c->outputConfig.TargetRectBottom = bottom;
+ c->outputConfig.BackgroundAlpha = alpha;
+ c->outputConfig.BackgroundR = red;
+ c->outputConfig.BackgroundG = green;
+ c->outputConfig.BackgroundB = blue;
+
+ c->outputSurfaceConfig.OutPixelFormat = output->format;
+ c->outputSurfaceConfig.OutBlkKind = output->kind;
+ c->outputSurfaceConfig.OutBlkHeight = 0;
+ c->outputSurfaceConfig.OutSurfaceWidth = output->width - 1;
+ c->outputSurfaceConfig.OutSurfaceHeight = output->height - 1;
+ c->outputSurfaceConfig.OutLumaWidth = output->stride - 1;
+ c->outputSurfaceConfig.OutLumaHeight = output->height - 1;
+ c->outputSurfaceConfig.OutChromaWidth = 16383;
+ c->outputSurfaceConfig.OutChromaHeight = 16383;
+
+ drm_tegra_bo_unmap(vic->config.bo);
+
+ return 0;
+}
+
+static int vic42_blit(struct vic *v, struct vic_image *output,
+ struct vic_image *input)
+{
+ struct vic42 *vic = container_of(v, struct vic42, base);
+ SlotSurfaceConfig *surface;
+ SlotConfig *slot;
+ ConfigStruct *c;
+ int err;
+
+ err = drm_tegra_bo_map(vic->config.bo, (void **)&c);
+ if (err < 0) {
+ fprintf(stderr, "failed to map configuration structure: %s\n",
+ strerror(-err));
+ return err;
+ }
+
+ memset(c, 0, sizeof(*c));
+
+ c->outputConfig.TargetRectTop = 0;
+ c->outputConfig.TargetRectLeft = 0;
+ c->outputConfig.TargetRectRight = output->width - 1;
+ c->outputConfig.TargetRectBottom = output->height - 1;
+ c->outputConfig.BackgroundAlpha = 255;
+ c->outputConfig.BackgroundR = 1023;
+ c->outputConfig.BackgroundG = 1023;
+ c->outputConfig.BackgroundB = 1023;
+
+ c->outputSurfaceConfig.OutPixelFormat = output->format;
+ c->outputSurfaceConfig.OutBlkKind = output->kind;
+ c->outputSurfaceConfig.OutBlkHeight = 0;
+ c->outputSurfaceConfig.OutSurfaceWidth = output->width - 1;
+ c->outputSurfaceConfig.OutSurfaceHeight = output->height - 1;
+ c->outputSurfaceConfig.OutLumaWidth = output->stride - 1;
+ c->outputSurfaceConfig.OutLumaHeight = output->height - 1;
+ c->outputSurfaceConfig.OutChromaWidth = 16383;
+ c->outputSurfaceConfig.OutChromaHeight = 16383;
+
+ slot = &c->slotStruct[0].slotConfig;
+ slot->SlotEnable = 1;
+ slot->CurrentFieldEnable = 1;
+ slot->PlanarAlpha = 255;
+ slot->ConstantAlpha = 1;
+ slot->SourceRectLeft = 0 << 16;
+ slot->SourceRectRight = (input->width - 1) << 16;
+ slot->SourceRectTop = 0 << 16;
+ slot->SourceRectBottom = (input->height - 1) << 16;
+ slot->DestRectLeft = 0;
+ slot->DestRectRight = output->width - 1;
+ slot->DestRectTop = 0;
+ slot->DestRectBottom = output->height - 1;
+ slot->SoftClampHigh = 1023;
+
+ surface = &c->slotStruct[0].slotSurfaceConfig;
+ surface->SlotPixelFormat = input->format;
+ surface->SlotBlkKind = input->kind;
+ surface->SlotBlkHeight = 0; /* XXX */
+ surface->SlotCacheWidth = VIC_CACHE_WIDTH_64Bx4; /* XXX */
+ surface->SlotSurfaceWidth = input->width - 1;
+ surface->SlotSurfaceHeight = input->height - 1;
+ surface->SlotLumaWidth = input->stride - 1;
+ surface->SlotLumaHeight = input->height - 1;
+ surface->SlotChromaWidth = 16383;
+ surface->SlotChromaHeight = 16383;
+
+ drm_tegra_bo_unmap(vic->config.bo);
+
+ return 0;
+}
+
+static int vic42_flip(struct vic *v, struct vic_image *output,
+ struct vic_image *input)
+{
+ struct vic42 *vic = container_of(v, struct vic42, base);
+ SlotSurfaceConfig *surface;
+ SlotConfig *slot;
+ ConfigStruct *c;
+ int err;
+
+ err = drm_tegra_bo_map(vic->config.bo, (void **)&c);
+ if (err < 0) {
+ fprintf(stderr, "failed to map configuration structure: %s\n",
+ strerror(-err));
+ return err;
+ }
+
+ memset(c, 0, sizeof(*c));
+
+ c->outputConfig.TargetRectTop = 0;
+ c->outputConfig.TargetRectLeft = 0;
+ c->outputConfig.TargetRectRight = output->width - 1;
+ c->outputConfig.TargetRectBottom = output->height - 1;
+ c->outputConfig.BackgroundAlpha = 255;
+ c->outputConfig.BackgroundR = 1023;
+ c->outputConfig.BackgroundG = 1023;
+ c->outputConfig.BackgroundB = 1023;
+ c->outputConfig.OutputFlipY = 1;
+
+ c->outputSurfaceConfig.OutPixelFormat = output->format;
+ c->outputSurfaceConfig.OutBlkKind = output->kind;
+ c->outputSurfaceConfig.OutBlkHeight = 0;
+ c->outputSurfaceConfig.OutSurfaceWidth = output->width - 1;
+ c->outputSurfaceConfig.OutSurfaceHeight = output->height - 1;
+ c->outputSurfaceConfig.OutLumaWidth = output->stride - 1;
+ c->outputSurfaceConfig.OutLumaHeight = output->height - 1;
+ c->outputSurfaceConfig.OutChromaWidth = 16383;
+ c->outputSurfaceConfig.OutChromaHeight = 16383;
+
+ slot = &c->slotStruct[0].slotConfig;
+ slot->SlotEnable = 1;
+ slot->CurrentFieldEnable = 1;
+ slot->PlanarAlpha = 255;
+ slot->ConstantAlpha = 1;
|
|
[-]
[+]
|
Added |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/tegra/vic42.h
^
|
| @@ -0,0 +1,597 @@
+/*
+ * Copyright © 2018 NVIDIA Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef VIC42_H
+#define VIC42_H
+
+#include <stdint.h>
+
+#define NVC5B6_VIDEO_COMPOSITOR_SET_APPLICATION_ID 0x00000200
+#define NVC5B6_VIDEO_COMPOSITOR_EXECUTE 0x00000300
+#define NVC5B6_VIDEO_COMPOSITOR_SET_CONTROL_PARAMS 0x00000704
+#define NVC5B6_VIDEO_COMPOSITOR_SET_CONFIG_STRUCT_OFFSET 0x00000708
+#define NVC5B6_VIDEO_COMPOSITOR_SET_FILTER_STRUCT_OFFSET 0x0000070c
+#define NVC5B6_VIDEO_COMPOSITOR_SET_HIST_OFFSET 0x00000714
+#define NVC5B6_VIDEO_COMPOSITOR_SET_OUTPUT_SURFACE_LUMA_OFFSET 0x00000720
+#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE0_LUMA_OFFSET(slot) (0x00001200 + (slot) * 0x00000060)
+#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE0_CHROMA_U_OFFSET(slot) (0x00001204 + (slot) * 0x00000060)
+#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE0_CHROMA_V_OFFSET(slot) (0x00001208 + (slot) * 0x00000060)
+#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE1_LUMA_OFFSET(slot) (0x0000120c + (slot) * 0x00000060)
+#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE1_CHROMA_U_OFFSET(slot) (0x00001210 + (slot) * 0x00000060)
+#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE1_CHROMA_V_OFFSET(slot) (0x00001214 + (slot) * 0x00000060)
+#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE2_LUMA_OFFSET(slot) (0x00001218 + (slot) * 0x00000060)
+#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE2_CHROMA_U_OFFSET(slot) (0x0000121c + (slot) * 0x00000060)
+#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE2_CHROMA_V_OFFSET(slot) (0x00001220 + (slot) * 0x00000060)
+#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE3_LUMA_OFFSET(slot) (0x00001224 + (slot) * 0x00000060)
+#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE3_CHROMA_U_OFFSET(slot) (0x00001228 + (slot) * 0x00000060)
+#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE3_CHROMA_V_OFFSET(slot) (0x0000122c + (slot) * 0x00000060)
+#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE4_LUMA_OFFSET(slot) (0x00001230 + (slot) * 0x00000060)
+#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE4_CHROMA_U_OFFSET(slot) (0x00001234 + (slot) * 0x00000060)
+#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE4_CHROMA_V_OFFSET(slot) (0x00001238 + (slot) * 0x00000060)
+#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE5_LUMA_OFFSET(slot) (0x0000123c + (slot) * 0x00000060)
+#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE5_CHROMA_U_OFFSET(slot) (0x00001240 + (slot) * 0x00000060)
+#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE5_CHROMA_V_OFFSET(slot) (0x00001244 + (slot) * 0x00000060)
+#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE6_LUMA_OFFSET(slot) (0x00001248 + (slot) * 0x00000060)
+#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE6_CHROMA_U_OFFSET(slot) (0x0000124c + (slot) * 0x00000060)
+#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE6_CHROMA_V_OFFSET(slot) (0x00001250 + (slot) * 0x00000060)
+#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE7_LUMA_OFFSET(slot) (0x00001254 + (slot) * 0x00000060)
+#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE7_CHROMA_U_OFFSET(slot) (0x00001258 + (slot) * 0x00000060)
+#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE7_CHROMA_V_OFFSET(slot) (0x0000125c + (slot) * 0x00000060)
+
+typedef struct {
+ uint64_t SlotEnable : 1; /* 0 */
+ uint64_t DeNoise : 1; /* 1 */
+ uint64_t AdvancedDenoise : 1; /* 2 */
+ uint64_t CadenceDetect : 1; /* 3 */
+ uint64_t MotionMap : 1; /* 4 */
+ uint64_t MMapCombine : 1; /* 5 */
+ uint64_t IsEven : 1; /* 6 */
+ uint64_t ChromaEven : 1; /* 7 */
+ uint64_t CurrentFieldEnable : 1; /* 8 */
+ uint64_t PrevFieldEnable : 1; /* 9 */
+ uint64_t NextFieldEnable : 1; /* 10 */
+ uint64_t NextNrFieldEnable : 1; /* 11 */
+ uint64_t CurMotionFieldEnable : 1; /* 12 */
+ uint64_t PrevMotionFieldEnable : 1; /* 13 */
+ uint64_t PpMotionFieldEnable : 1; /* 14 */
+ uint64_t CombMotionFieldEnable : 1; /* 15 */
+ uint64_t FrameFormat : 4; /* 19..16 */
+ uint64_t FilterLengthY : 2; /* 21..20 */
+ uint64_t FilterLengthX : 2; /* 23..22 */
+ uint64_t Panoramic : 12; /* 35..24 */
+ uint64_t ChromaUpLengthY : 2; /* 37..36 */
+ uint64_t ChromaUpLengthX : 2; /* 39..38 */
+ uint64_t reserved1 : 18; /* 57..40 */
+ uint64_t DetailFltClamp : 6; /* 63..58 */
+ uint64_t FilterNoise : 10; /* 73..64 */
+ uint64_t FilterDetail : 10; /* 83..74 */
+ uint64_t ChromaNoise : 10; /* 93..84 */
+ uint64_t ChromaDetail : 10; /* 103..94 */
+ uint64_t DeinterlaceMode : 4; /* 107..104 */
+ uint64_t MotionAccumWeight : 3; /* 110..108 */
+ uint64_t NoiseIir : 11; /* 121..111 */
+ uint64_t LightLevel : 4; /* 125..122 */
+ uint64_t reserved4 : 2; /* 127..126 */
+ /* 128 */
+ uint64_t SoftClampLow : 10; /* 9..0 */
+ uint64_t SoftClampHigh : 10; /* 19..10 */
+ uint64_t reserved5 : 12; /* 31..20 */
+ uint64_t reserved6 : 2; /* 33..32 */
+ uint64_t PlanarAlpha : 8; /* 41..34 */
+ uint64_t ConstantAlpha : 1; /* 42 */
+ uint64_t StereoInterleave : 3; /* 45..43 */
+ uint64_t ClipEnabled : 1; /* 46 */
+ uint64_t ClearRectMask : 8; /* 54..47 */
+ uint64_t DegammaMode : 2; /* 56..55 */
+ uint64_t reserved7 : 1; /* 57 */
+ uint64_t DecompressEnable : 1; /* 58 */
+ uint64_t DecompressKind : 4; /* 62..59 */
+ uint64_t reserved9 : 1; /* 63 */
+ uint64_t DecompressCtbCount : 8; /* 71..64 */
+ uint64_t DecompressZbcColor : 32; /* 103..72 */
+ uint64_t reserved12 : 24; /* 127..104 */
+ /* 256 */
+ uint64_t SourceRectLeft : 30; /* 29..0 */
+ uint64_t reserved14 : 2; /* 31..30 */
+ uint64_t SourceRectRight : 30; /* 61..32 */
+ uint64_t reserved15 : 2; /* 63..62 */
+ uint64_t SourceRectTop : 30; /* 93..64 */
+ uint64_t reserved16 : 2; /* 95..94 */
+ uint64_t SourceRectBottom : 30; /* 125..96 */
+ uint64_t reserved17 : 2; /* 127..126 */
+ /* 384 */
+ uint64_t DestRectLeft : 14; /* 13..0 */
+ uint64_t reserved18 : 2; /* 15..14 */
+ uint64_t DestRectRight : 14; /* 29..16 */
+ uint64_t reserved19 : 2; /* 31..30 */
+ uint64_t DestRectTop : 14; /* 45..32 */
+ uint64_t reserved20 : 2; /* 47..46 */
+ uint64_t DestRectBottom : 14; /* 61..48 */
+ uint64_t reserved21 : 2; /* 63..62 */
+ uint64_t B16ScalerEnable : 1; /* 64 */
+ uint64_t reserved22 : 31; /* 95..65 */
+ uint64_t reserved23 : 32; /* 127..96 */
+} SlotConfig;
+
+typedef struct {
+ uint64_t SlotPixelFormat : 7; /* 6..0 */
+ uint64_t SlotChromaLocHORIZ : 2; /* 8..7 */
+ uint64_t SlotChromaLocVert : 2; /* 10..9 */
+ uint64_t SlotBlkKind : 4; /* 14..11 */
+ uint64_t SlotBlkHeight : 4; /* 18..15 */
+ uint64_t SlotCacheWidth : 3; /* 21..19 */
+ uint64_t reserved0 : 10; /* 31..22 */
+ uint64_t SlotSurfaceWidth : 14; /* 45..32 */
+ uint64_t SlotSurfaceHeight : 14; /* 59..46 */
+ uint64_t reserved1 : 4; /* 63..60 */
+ uint64_t SlotLumaWidth : 14; /* 77..64 */
+ uint64_t SlotLumaHeight : 14; /* 91..78 */
+ uint64_t reserved2 : 4; /* 95..92 */
+ uint64_t SlotChromaWidth : 14; /* 109..96 */
+ uint64_t SlotChromaHeight : 14; /* 123..110 */
+ uint64_t reserved3 : 4; /* 127..124 */
+} SlotSurfaceConfig;
+
+typedef struct {
+ uint64_t luma_coeff0 : 20; /* 19..0 */
+ uint64_t luma_coeff1 : 20; /* 39..20 */
+ uint64_t luma_coeff2 : 20; /* 59..40 */
+ uint64_t luma_r_shift : 4; /* 63..60 */
+ uint64_t luma_coeff3 : 20; /* 83..64 */
+ uint64_t LumaKeyLower : 10; /* 93..84 */
+ uint64_t LumaKeyUpper : 10; /* 103..94 */
+ uint64_t LumaKeyEnabled : 1; /* 104 */
+ uint64_t reserved0 : 2; /* 106..105 */
+ uint64_t reserved1 : 21; /* 127..107 */
+} LumaKeyStruct;
+
+typedef struct {
+ uint64_t matrix_coeff00 : 20; /* 19..0 */
+ uint64_t matrix_coeff10 : 20; /* 39..20 */
+ uint64_t matrix_coeff20 : 20; /* 59..40 */
+ uint64_t matrix_r_shift : 4; /* 63..60 */
+ uint64_t matrix_coeff01 : 20; /* 83..64 */
+ uint64_t matrix_coeff11 : 20; /* 103..84 */
+ uint64_t matrix_coeff21 : 20; /* 123..104 */
+ uint64_t reserved0 : 3; /* 126..124 */
+ uint64_t matrix_enable : 1; /* 127 */
+ /* 128 */
+ uint64_t matrix_coeff02 : 20; /* 19..0 */
+ uint64_t matrix_coeff12 : 20; /* 39..20 */
+ uint64_t matrix_coeff22 : 20; /* 59..40 */
+ uint64_t reserved1 : 4; /* 63..60 */
+ uint64_t matrix_coeff03 : 20; /* 83..64 */
+ uint64_t matrix_coeff13 : 20; /* 103..84 */
+ uint64_t matrix_coeff23 : 20; /* 123..104 */
+ uint64_t reserved2 : 4; /* 127..124 */
+} MatrixStruct;
+
+typedef struct {
+ uint64_t ClearRect0Left : 14; /* 13..0 */
+ uint64_t reserved0 : 2; /* 15..14 */
+ uint64_t ClearRect0Right : 14; /* 29..16 */
+ uint64_t reserved1 : 2; /* 31..30 */
+ uint64_t ClearRect0Top : 14; /* 45..32 */
+ uint64_t reserved2 : 2; /* 47..46 */
+ uint64_t ClearRect0Bottom : 14; /* 61..48 */
+ uint64_t reserved3 : 2; /* 63..62 */
+ uint64_t ClearRect1Left : 14; /* 77..64 */
+ uint64_t reserved4 : 2; /* 79..78 */
+ uint64_t ClearRect1Right : 14; /* 93..80 */
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/util/kms.c
^
|
| @@ -96,33 +96,6 @@
ARRAY_SIZE(connector_status_names));
}
-static const struct type_name connector_type_names[] = {
- { DRM_MODE_CONNECTOR_Unknown, "unknown" },
- { DRM_MODE_CONNECTOR_VGA, "VGA" },
- { DRM_MODE_CONNECTOR_DVII, "DVI-I" },
- { DRM_MODE_CONNECTOR_DVID, "DVI-D" },
- { DRM_MODE_CONNECTOR_DVIA, "DVI-A" },
- { DRM_MODE_CONNECTOR_Composite, "composite" },
- { DRM_MODE_CONNECTOR_SVIDEO, "s-video" },
- { DRM_MODE_CONNECTOR_LVDS, "LVDS" },
- { DRM_MODE_CONNECTOR_Component, "component" },
- { DRM_MODE_CONNECTOR_9PinDIN, "9-pin DIN" },
- { DRM_MODE_CONNECTOR_DisplayPort, "DP" },
- { DRM_MODE_CONNECTOR_HDMIA, "HDMI-A" },
- { DRM_MODE_CONNECTOR_HDMIB, "HDMI-B" },
- { DRM_MODE_CONNECTOR_TV, "TV" },
- { DRM_MODE_CONNECTOR_eDP, "eDP" },
- { DRM_MODE_CONNECTOR_VIRTUAL, "Virtual" },
- { DRM_MODE_CONNECTOR_DSI, "DSI" },
- { DRM_MODE_CONNECTOR_DPI, "DPI" },
-};
-
-const char *util_lookup_connector_type_name(unsigned int type)
-{
- return util_lookup_type_name(type, connector_type_names,
- ARRAY_SIZE(connector_type_names));
-}
-
static const char * const modules[] = {
"i915",
"amdgpu",
@@ -150,6 +123,8 @@
"komeda",
"imx-dcss",
"mxsfb-drm",
+ "simpledrm",
+ "imx-lcdif",
};
int util_open(const char *device, const char *module)
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/tests/util/kms.h
^
|
| @@ -28,7 +28,6 @@
const char *util_lookup_encoder_type_name(unsigned int type);
const char *util_lookup_connector_status_name(unsigned int type);
-const char *util_lookup_connector_type_name(unsigned int type);
int util_open(const char *device, const char *module);
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/xf86atomic.h
^
|
| @@ -108,7 +108,7 @@
c = atomic_read(v);
while (c != unless && (old = atomic_cmpxchg(v, c, c + add)) != c)
c = old;
- return c == unless;
+ return c != unless;
}
#endif
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/xf86drm.c
^
|
| @@ -175,11 +175,15 @@
static char *
drmGetFormatModifierNameFromAmlogic(uint64_t modifier);
+static char *
+drmGetFormatModifierNameFromVivante(uint64_t modifier);
+
static const struct drmVendorInfo modifier_format_vendor_table[] = {
{ DRM_FORMAT_MOD_VENDOR_ARM, drmGetFormatModifierNameFromArm },
{ DRM_FORMAT_MOD_VENDOR_NVIDIA, drmGetFormatModifierNameFromNvidia },
{ DRM_FORMAT_MOD_VENDOR_AMD, drmGetFormatModifierNameFromAmd },
{ DRM_FORMAT_MOD_VENDOR_AMLOGIC, drmGetFormatModifierNameFromAmlogic },
+ { DRM_FORMAT_MOD_VENDOR_VIVANTE, drmGetFormatModifierNameFromVivante },
};
#ifndef AFBC_FORMAT_MOD_MODE_VALUE_MASK
@@ -261,6 +265,7 @@
static bool
drmGetAfrcFormatModifierNameFromArm(uint64_t modifier, FILE *fp)
{
+ bool scan_layout;
for (unsigned int i = 0; i < 2; ++i) {
uint64_t coding_unit_block =
(modifier >> (i * 4)) & AFRC_FORMAT_MOD_CU_SIZE_MASK;
@@ -292,7 +297,7 @@
}
}
- bool scan_layout =
+ scan_layout =
(modifier & AFRC_FORMAT_MOD_LAYOUT_SCAN) == AFRC_FORMAT_MOD_LAYOUT_SCAN;
if (scan_layout) {
fprintf(fp, "SCAN");
@@ -473,6 +478,9 @@
case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS:
str_tile_version = "GFX10_RBPLUS";
break;
+ case AMD_FMT_MOD_TILE_VER_GFX11:
+ str_tile_version = "GFX11";
+ break;
}
if (str_tile_version) {
@@ -500,6 +508,9 @@
case AMD_FMT_MOD_TILE_GFX9_64K_R_X:
str_tile = "GFX9_64K_R_X";
break;
+ case AMD_FMT_MOD_TILE_GFX11_256K_R_X:
+ str_tile = "GFX11_256K_R_X";
+ break;
}
if (str_tile)
@@ -546,6 +557,70 @@
return mod_amlogic;
}
+static char *
+drmGetFormatModifierNameFromVivante(uint64_t modifier)
+{
+ const char *color_tiling, *tile_status, *compression;
+ char *mod_vivante = NULL;
+
+ switch (modifier & VIVANTE_MOD_TS_MASK) {
+ case 0:
+ tile_status = "";
+ break;
+ case VIVANTE_MOD_TS_64_4:
+ tile_status = ",TS=64B_4";
+ break;
+ case VIVANTE_MOD_TS_64_2:
+ tile_status = ",TS=64B_2";
+ break;
+ case VIVANTE_MOD_TS_128_4:
+ tile_status = ",TS=128B_4";
+ break;
+ case VIVANTE_MOD_TS_256_4:
+ tile_status = ",TS=256B_4";
+ break;
+ default:
+ tile_status = ",TS=UNKNOWN";
+ break;
+ }
+
+ switch (modifier & VIVANTE_MOD_COMP_MASK) {
+ case 0:
+ compression = "";
+ break;
+ case VIVANTE_MOD_COMP_DEC400:
+ compression = ",COMP=DEC400";
+ break;
+ default:
+ compression = ",COMP=UNKNOWN";
+ break;
+ }
+
+ switch (modifier & ~VIVANTE_MOD_EXT_MASK) {
+ case 0:
+ color_tiling = "LINEAR";
+ break;
+ case DRM_FORMAT_MOD_VIVANTE_TILED:
+ color_tiling = "TILED";
+ break;
+ case DRM_FORMAT_MOD_VIVANTE_SUPER_TILED:
+ color_tiling = "SUPER_TILED";
+ break;
+ case DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED:
+ color_tiling = "SPLIT_TILED";
+ break;
+ case DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED:
+ color_tiling = "SPLIT_SUPER_TILED";
+ break;
+ default:
+ color_tiling = "UNKNOWN";
+ break;
+ }
+
+ asprintf(&mod_vivante, "%s%s%s", color_tiling, tile_status, compression);
+ return mod_vivante;
+}
+
static unsigned log2_int(unsigned x)
{
unsigned l;
@@ -848,7 +923,7 @@
}
#endif
- fd = open(buf, O_RDWR | O_CLOEXEC, 0);
+ fd = open(buf, O_RDWR | O_CLOEXEC);
drmMsg("drmOpenDevice: open result is %d, (%s)\n",
fd, fd < 0 ? strerror(errno) : "OK");
if (fd >= 0)
@@ -868,7 +943,7 @@
chmod(buf, devmode);
}
}
- fd = open(buf, O_RDWR | O_CLOEXEC, 0);
+ fd = open(buf, O_RDWR | O_CLOEXEC);
drmMsg("drmOpenDevice: open result is %d, (%s)\n",
fd, fd < 0 ? strerror(errno) : "OK");
if (fd >= 0)
@@ -906,7 +981,7 @@
return -EINVAL;
sprintf(buf, dev_name, DRM_DIR_NAME, minor);
- if ((fd = open(buf, O_RDWR | O_CLOEXEC, 0)) >= 0)
+ if ((fd = open(buf, O_RDWR | O_CLOEXEC)) >= 0)
return fd;
return -errno;
}
@@ -1134,7 +1209,7 @@
int retcode;
sprintf(proc_name, "/proc/dri/%d/name", i);
- if ((fd = open(proc_name, O_RDONLY, 0)) >= 0) {
+ if ((fd = open(proc_name, O_RDONLY)) >= 0) {
retcode = read(fd, buf, sizeof(buf)-1);
close(fd);
if (retcode) {
@@ -3891,7 +3966,7 @@
if (get_sysctl_pci_bus_info(maj, min, &info) != 0)
return -EINVAL;
- fd = open("/dev/pci", O_RDONLY, 0);
+ fd = open("/dev/pci", O_RDONLY);
if (fd < 0)
return -errno;
@@ -5105,3 +5180,43 @@
return modifier_found;
}
+
+/**
+ * Get a human-readable name for a DRM FourCC format.
+ *
+ * \param format The format.
+ * \return A malloc'ed string containing the format name. Caller is responsible
+ * for freeing it.
+ */
+drm_public char *
+drmGetFormatName(uint32_t format)
+{
+ char *str, code[5];
+ const char *be;
+ size_t str_size, i;
+
+ be = (format & DRM_FORMAT_BIG_ENDIAN) ? "_BE" : "";
+ format &= ~DRM_FORMAT_BIG_ENDIAN;
+
+ if (format == DRM_FORMAT_INVALID)
+ return strdup("INVALID");
+
+ code[0] = (char) ((format >> 0) & 0xFF);
+ code[1] = (char) ((format >> 8) & 0xFF);
+ code[2] = (char) ((format >> 16) & 0xFF);
+ code[3] = (char) ((format >> 24) & 0xFF);
+ code[4] = '\0';
+
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/xf86drm.h
^
|
| @@ -954,6 +954,9 @@
extern char *
drmGetFormatModifierName(uint64_t modifier);
+extern char *
+drmGetFormatName(uint32_t format);
+
#ifndef fourcc_mod_get_vendor
#define fourcc_mod_get_vendor(modifier) \
(((modifier) >> 56) & 0xff)
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/xf86drmMode.c
^
|
| @@ -610,6 +610,29 @@
return _drmModeGetConnector(fd, connector_id, 0);
}
+drm_public uint32_t drmModeConnectorGetPossibleCrtcs(int fd,
+ const drmModeConnector *connector)
+{
+ drmModeEncoder *encoder;
+ int i;
+ uint32_t possible_crtcs;
+
+ possible_crtcs = 0;
+ for (i = 0; i < connector->count_encoders; i++) {
+ encoder = drmModeGetEncoder(fd, connector->encoders[i]);
+ if (!encoder) {
+ return 0;
+ }
+
+ possible_crtcs |= encoder->possible_crtcs;
+ drmModeFreeEncoder(encoder);
+ }
+
+ if (possible_crtcs == 0)
+ errno = ENOENT;
+ return possible_crtcs;
+}
+
drm_public int drmModeAttachMode(int fd, uint32_t connector_id, drmModeModeInfoPtr mode_info)
{
struct drm_mode_mode_cmd res;
@@ -1348,7 +1371,7 @@
return req;
}
-drm_public drmModeAtomicReqPtr drmModeAtomicDuplicate(drmModeAtomicReqPtr old)
+drm_public drmModeAtomicReqPtr drmModeAtomicDuplicate(const drmModeAtomicReqPtr old)
{
drmModeAtomicReqPtr new;
@@ -1378,7 +1401,7 @@
}
drm_public int drmModeAtomicMerge(drmModeAtomicReqPtr base,
- drmModeAtomicReqPtr augment)
+ const drmModeAtomicReqPtr augment)
{
uint32_t i;
@@ -1411,7 +1434,7 @@
return 0;
}
-drm_public int drmModeAtomicGetCursor(drmModeAtomicReqPtr req)
+drm_public int drmModeAtomicGetCursor(const drmModeAtomicReqPtr req)
{
if (!req)
return -EINVAL;
@@ -1480,7 +1503,7 @@
return first->cursor - second->cursor;
}
-drm_public int drmModeAtomicCommit(int fd, drmModeAtomicReqPtr req,
+drm_public int drmModeAtomicCommit(int fd, const drmModeAtomicReqPtr req,
uint32_t flags, void *user_data)
{
drmModeAtomicReqPtr sorted;
@@ -1747,3 +1770,105 @@
{
drmFree(ptr);
}
+
+drm_public const char *
+drmModeGetConnectorTypeName(uint32_t connector_type)
+{
+ /* Keep the strings in sync with the kernel's drm_connector_enum_list in
+ * drm_connector.c. */
+ switch (connector_type) {
+ case DRM_MODE_CONNECTOR_Unknown:
+ return "Unknown";
+ case DRM_MODE_CONNECTOR_VGA:
+ return "VGA";
+ case DRM_MODE_CONNECTOR_DVII:
+ return "DVI-I";
+ case DRM_MODE_CONNECTOR_DVID:
+ return "DVI-D";
+ case DRM_MODE_CONNECTOR_DVIA:
+ return "DVI-A";
+ case DRM_MODE_CONNECTOR_Composite:
+ return "Composite";
+ case DRM_MODE_CONNECTOR_SVIDEO:
+ return "SVIDEO";
+ case DRM_MODE_CONNECTOR_LVDS:
+ return "LVDS";
+ case DRM_MODE_CONNECTOR_Component:
+ return "Component";
+ case DRM_MODE_CONNECTOR_9PinDIN:
+ return "DIN";
+ case DRM_MODE_CONNECTOR_DisplayPort:
+ return "DP";
+ case DRM_MODE_CONNECTOR_HDMIA:
+ return "HDMI-A";
+ case DRM_MODE_CONNECTOR_HDMIB:
+ return "HDMI-B";
+ case DRM_MODE_CONNECTOR_TV:
+ return "TV";
+ case DRM_MODE_CONNECTOR_eDP:
+ return "eDP";
+ case DRM_MODE_CONNECTOR_VIRTUAL:
+ return "Virtual";
+ case DRM_MODE_CONNECTOR_DSI:
+ return "DSI";
+ case DRM_MODE_CONNECTOR_DPI:
+ return "DPI";
+ case DRM_MODE_CONNECTOR_WRITEBACK:
+ return "Writeback";
+ case DRM_MODE_CONNECTOR_SPI:
+ return "SPI";
+ case DRM_MODE_CONNECTOR_USB:
+ return "USB";
+ default:
+ return NULL;
+ }
+}
+
+drm_public int
+drmModeCreateDumbBuffer(int fd, uint32_t width, uint32_t height, uint32_t bpp,
+ uint32_t flags, uint32_t *handle, uint32_t *pitch,
+ uint64_t *size)
+{
+ int ret;
+ struct drm_mode_create_dumb create = {
+ .width = width,
+ .height = height,
+ .bpp = bpp,
+ .flags = flags,
+ };
+
+ ret = DRM_IOCTL(fd, DRM_IOCTL_MODE_CREATE_DUMB, &create);
+ if (ret != 0)
+ return ret;
+
+ *handle = create.handle;
+ *pitch = create.pitch;
+ *size = create.size;
+ return 0;
+}
+
+drm_public int
+drmModeDestroyDumbBuffer(int fd, uint32_t handle)
+{
+ struct drm_mode_destroy_dumb destroy = {
+ .handle = handle,
+ };
+
+ return DRM_IOCTL(fd, DRM_IOCTL_MODE_DESTROY_DUMB, &destroy);
+}
+
+drm_public int
+drmModeMapDumbBuffer(int fd, uint32_t handle, uint64_t *offset)
+{
+ int ret;
+ struct drm_mode_map_dumb map = {
+ .handle = handle,
+ };
+
+ ret = DRM_IOCTL(fd, DRM_IOCTL_MODE_MAP_DUMB, &map);
+ if (ret != 0)
+ return ret;
+
+ *offset = map.offset;
+ return 0;
+}
|
|
[-]
[+]
|
Changed |
_service:tar_git:libdrm-2.4.115+git1.tar.bz2/upstream/xf86drmMode.h
^
|
| @@ -381,6 +381,19 @@
uint32_t connector_id);
/**
+ * Get a bitmask of CRTCs a connector is compatible with.
+ *
+ * The bits reference CRTC indices. If the n-th CRTC is compatible with the
+ * connector, the n-th bit will be set. The indices are taken from the array
+ * returned by drmModeGetResources(). The indices are different from the object
+ * IDs.
+ *
+ * Zero is returned on error.
+ */
+extern uint32_t drmModeConnectorGetPossibleCrtcs(int fd,
+ const drmModeConnector *connector);
+
+/**
* Attaches the given mode to an connector.
*/
extern int drmModeAttachMode(int fd, uint32_t connectorId, drmModeModeInfoPtr mode_info);
@@ -433,18 +446,18 @@
typedef struct _drmModeAtomicReq drmModeAtomicReq, *drmModeAtomicReqPtr;
extern drmModeAtomicReqPtr drmModeAtomicAlloc(void);
-extern drmModeAtomicReqPtr drmModeAtomicDuplicate(drmModeAtomicReqPtr req);
+extern drmModeAtomicReqPtr drmModeAtomicDuplicate(const drmModeAtomicReqPtr req);
extern int drmModeAtomicMerge(drmModeAtomicReqPtr base,
- drmModeAtomicReqPtr augment);
+ const drmModeAtomicReqPtr augment);
extern void drmModeAtomicFree(drmModeAtomicReqPtr req);
-extern int drmModeAtomicGetCursor(drmModeAtomicReqPtr req);
+extern int drmModeAtomicGetCursor(const drmModeAtomicReqPtr req);
extern void drmModeAtomicSetCursor(drmModeAtomicReqPtr req, int cursor);
extern int drmModeAtomicAddProperty(drmModeAtomicReqPtr req,
uint32_t object_id,
uint32_t property_id,
uint64_t value);
extern int drmModeAtomicCommit(int fd,
- drmModeAtomicReqPtr req,
+ const drmModeAtomicReqPtr req,
uint32_t flags,
void *user_data);
@@ -475,6 +488,47 @@
extern int drmModeRevokeLease(int fd, uint32_t lessee_id);
+/**
+ * Get a string describing a connector type.
+ *
+ * NULL is returned if the connector type is unsupported. Callers should handle
+ * this gracefully, e.g. by falling back to "Unknown" or printing the raw value.
+ */
+extern const char *
+drmModeGetConnectorTypeName(uint32_t connector_type);
+
+/**
+ * Create a dumb buffer.
+ *
+ * Given a width, height and bits-per-pixel, the kernel will return a buffer
+ * handle, pitch and size. The flags must be zero.
+ *
+ * Returns 0 on success, negative errno on error.
+ */
+extern int
+drmModeCreateDumbBuffer(int fd, uint32_t width, uint32_t height, uint32_t bpp,
+ uint32_t flags, uint32_t *handle, uint32_t *pitch,
+ uint64_t *size);
+
+/**
+ * Destroy a dumb buffer.
+ *
+ * Returns 0 on success, negative errno on error.
+ */
+extern int
+drmModeDestroyDumbBuffer(int fd, uint32_t handle);
+
+/**
+ * Prepare a dumb buffer for mapping.
+ *
+ * The kernel returns an offset which can be used as an argument to mmap(2) on
+ * the DRM FD.
+ *
+ * Returns 0 on success, negative errno on error.
+ */
+extern int
+drmModeMapDumbBuffer(int fd, uint32_t handle, uint64_t *offset);
+
#if defined(__cplusplus)
}
#endif
|
